W9816G6JH-6 datasheet(5/42 Pages) WINBOND

Part #	W9816G6JH-6

Description	512K X 2 BANKS X 16 BITS SDRAM

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Manufacturer	WINBOND [Winbond]

Direct Link	http://www.winbond.com

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W9816G6JH

Publication Release Date: Jun. 24, 2014

- 5 -

Revision: A01

5.

PIN DESCRIPTION

PIN NUMBER

PIN NAME

FUNCTION

DESCRIPTION

20

24,

27

32

A0

A10

Address

Multiplexed pins for row and column address.

Row address: A0

A10. Column address: A0A7.

19

BA

Bank Select

Select bank to activate during row address latch time,

or bank to read/write during column address latch

time.

2, 3, 5, 6, 8, 9,

11, 12, 39, 40,

42, 43, 45, 46,

48, 49

DQ0

DQ15

Data

Input/ Output

Multiplexed pins for data input and output.

18

CS

Chip Select

Disable or enable the command decoder. When

command decoder is disabled, new command is

ignored and previous operation continues.

17

R A S

Row Address

Strobe

Command input. When sampled at the rising edge of

the clock, R A S , C A S and WE define the operation

to be executed.

16

C A S

Column

Address Strobe Referred to

R A S

15

WE

Write Enable

Referred to R A S

36, 14

UDQM/

LDQM

Input/Output

Mask

The output buffer is placed at Hi-Z (with latency of 2)

when DQM is sampled high in read cycle. In write

cycle, sampling DQM high will block the write

operation with zero latency.

35

CLK

Clock Inputs

System clock used to sample inputs on the rising

edge of clock.

34

CKE

Clock Enable

CKE controls the clock activation and deactivation.

When CKE is low, Power Down mode, Suspend

mode, or Self Refresh mode is entered.

1, 25

VDD

Power

Power for input buffers and logic circuit inside DRAM.

26, 50

VSS

Ground

Ground for input buffers and logic circuit inside

DRAM.

7, 13, 38, 44,

VDDQ

Power for I/O

buffer

Separated power from VDD, used for output buffers to

improve noise immunity.

4, 10, 41, 47

VSSQ

Ground for I/O

buffer

Separated ground from VSS, used for output buffers

to improve noise immunity.

33, 37

NC

No Connection No connection.

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