Electronic Components Datasheet Search |
|
ADMC201 Datasheet(PDF) 3 Page - Analog Devices |
|
ADMC201 Datasheet(HTML) 3 Page - Analog Devices |
3 / 15 page ADMC201 REV. B –3– 9 Table I. Timing Specifications (VDD = 5 V, 5%; TA = –40 C to +85 C) Number Symbol Timing Requirements Min Max Units 1tperclk CLK Period 40 160 ns 2tpwhclk CLK Pulsewidth, High 20 ns 3tpwlclk CLK Pulsewidth, Low 20 ns 4tsucsb_wrb CS Low before Falling Edge of WR 0ns 5tsuaddr_wrb ADDR Valid before Falling Edge of WR 0ns 6tsudata_wrb DATA Valid before Rising Edge of WR 13 ns 7thdwrb_data DATA Hold after Rising Edge of WR 4.5 ns 8thdwrb_addr ADDR Hold after Rising Edge of WR 4.5 ns 9thdwrb_csb CS Hold after Rising Edge of WR 4.5 ns 10 tpwlwrb 1 WR Pulsewidth, Low 20 ns 11 tpwhwrb 1 WR Pulsewidth, High 20 ns 12 thdwrb_clk_h 1 WR Low after Rising Edge of CLK 7 ns 13 tsuwrb_clk_h 1 WR High before Rising Edge of CLK 7 ns 14 tsuwrb_clk_l 1 WR High before Falling Edge of CLK 10 ns 15 thdclk_wrb_l 1 WR High after Falling Edge of CLK 10 ns 16 tsucsb_rdb CS Low before Falling Edge of RD 0ns 17 tsuaddr_rdb ADDR Valid before Falling Edge of RD 0ns 18 thdrdb_addr ADDR Hold after Rising Edge of RD 0ns 19 thdrdb_csb CS Hold after Rising Edge of RD 0ns 20 tpwlrdb RD Pulsewidth, Low 20 ns 21 tpwhrdb RD Pulsewidth, High 20 ns 22 tsurdb_clk_h RD Low before Rising Edge of CLK 7.5 ns 23 thdrdb_clk_h RD Low after Rising Edge of CLK 7.5 ns 24 tpwlresetb RESET Pulsewidth, Low 2 × t perclk ns NOTE 1All WRITES to the ADMC201 must occur within 1 System Clock Cycle (0 wait states). Number Symbol Switching Characteristics Min Max Units 25 tdlyrdb_data DATA Valid after Falling Edge of RD 23 ns 26 thdrdb_data DATA Hold after Rising Edge of RD 0ns 27 tpwh_pio Digital I/O Pulsewidth, High 2 × tperclk ns 28 tpwl_pio Digital I/O Pulsewidth, Low 2 × tperclk ns 1 2 3 CLK Figure 1. Clock Input Timing RESET 24 CLK Figure 2. Reset Input Timing 11 4 5 6 7 10 12 15 13 9 8 14 CLK CS A0–A3 WR DATA NOTE: ALL WRITES TO THE ADMC201 MUST OCCUR WITHIN ONE SYSTEM CLOCK CYCLE (i.e., 0 WAIT STATES) Figure 3. Write Cycle Timing Diagram |
Similar Part No. - ADMC201_15 |
|
Similar Description - ADMC201_15 |
|
|
Link URL |
Privacy Policy |
ALLDATASHEET.NET |
Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
Family Site : ic2ic.com |
icmetro.com |