Data Sheet

ADN2850

Rev. E | Page 9 of 28

PIN 1

INDICATOR

1

SDO

2

GND

3

4

11 WP

12 PR

ADN2850

NOTES

1. THE EXPOSED PAD IS LEFT FLOATING

TOP VIEW

(Not to Scale)

(EXPOSED

PAD)

Figure 5. Pin Configuration

Table 5. Pin Function Descriptions

Pin No.

Mnemonic

Description

1

SDO

Serial Data Output. Serves readback and daisy-chain functions. Command 9 and Command 10 activate the SDO

output for the readback function, delayed by 24 or 25 clock pulses, depending on the clock polarity before and

after the data-word (see Figure 2 and Figure 3). In other commands, the SDO shifts out the previously loaded SDI

bit pattern, delayed by 24 or 25 clock pulses depending on the clock polarity (see Figure 2 and Figure 3). This

previously shifted out SDI can be used for daisy-chaining multiple devices. Whenever SDO is used, a pull-up

resistor in the range of 1 kΩ to 10 kΩ is needed.

2

GND

Ground Pin, Logic Ground Reference.

3

2 mA for 15 ms when storing data to EEMEM.

4

V1

Log Output Voltage 1. Generates voltage from an internal diode configured transistor.

5

W1

Wiper terminal of RDAC1. ADDR (RDAC1) = 0x0.

6

B1

Terminal B of RDAC1.

7

B2

Terminal B of RDAC2.

8

W2

Wiper terminal of RDAC2. ADDR (RDAC2) = 0x1.

9

V2

Log Output Voltage 2. Generates voltage from an internal diode configured transistor.

10

Positive Power Supply.

11

A

Optional Write Protect. When active low,

A

A

prevents any changes to the present contents, except

A

A

strobe.

CMD_1 and COMD_8 refresh the RDAC register from EEMEM. Tie

A

A

12

A

Optional Hardware Override Preset. Refreshes the scratchpad register with current contents of the EEMEM

register. Factory default loads midscale until EEMEM is loaded with a new value by the user.

A

A

is activated

at the logic high transition. Tie

A

A

13

A

Serial Register Chip Select Active Low. Serial register operation takes place when

A

A

returns to logic high.

14

RDY

Ready. Active high open-drain output. Identifies completion of Instruction 2, Instruction 3, Instruction 8,

Instruction 9, Instruction 10, and

A

A

.

15

CLK

Serial Input Register Clock. Shifts in one bit at a time on positive clock edges.

16

SDI

Serial Data Input. Shifts in one bit at a time on positive clock CLK edges. MSB loads first.

EP