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ADP1823 Datasheet(PDF) 8 Page - Analog Devices |
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ADP1823 Datasheet(HTML) 8 Page - Analog Devices |
8 / 32 page ADP1823 Rev. D | Page 8 of 32 Pin No. Mnemonic Description 24 POK1 Open-Drain Power OK Output for Channel 1. Sinks current when FB1 is out of regulation. Connect a pull-up resistor from POK1 to VREG. 25 EN1 Enable Input for Channel 1. Drive EN1 high to turn on the Channel 1 controller, and drive it low to turn off the Channel 1 controller. Enabling starts the internal LDO. Tie to IN for automatic startup. 26 EN2 Enable Input for Channel 2. Drive EN2 high to turn on the Channel 2 controller, and drive it low to turn off the Channel 2 controller. Enabling starts the internal LDO. Tie to IN for automatic startup. 27 LDOSD LDO Shut-Down Input. Only used to shut down the LDO in those applications where IN is tied directly to VREG. Otherwise, connect LDOSD to GND or leave it open because it has an internal 100 kΩ pull-down resistor. 28 IN Input Supply to the Internal Linear Regulator. Drive IN with 5.5 V to 20 V to power the ADP1823 from the LDO. For input voltages between 3.7 V and 5.5 V, tie IN to VREG and PV. 29 VREG Output of the Internal Linear Regulator (LDO). The internal circuitry and gate drivers are powered from VREG. Bypass VREG to the ground plane with a 1 μF ceramic capacitor. 30 SS1 Soft Start Control Input. Connect a capacitor from SS1 to GND to set the soft start period. 31 TRK1 Tracking Input for Channel 1. To track a master voltage, drive TRK1 from a voltage divider to the master voltage. If the tracking function is not used, connect TRK1 to VREG. 32 COMP1 Error Amplifier Output for Channel 1. Connect an RC network from COMP1 to FB1 to compensate Channel 1. |
Similar Part No. - ADP1823_15 |
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Similar Description - ADP1823_15 |
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