EN27LN2G08 datasheet(11/56 Pages) EON

Part #	EN27LN2G08

Description	2 Gigabit (256M x 8), 3.3 V NAND Flash Memory

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Manufacturer	EON [Eon Silicon Solution Inc.]

Direct Link	http://www.essi.com.tw

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This Data Sheet may be revised by subsequent versions

or modifications due to changes in technical specifications.

11

EN27LN2G08

Rev. D, Issue Date: 2013/12/13

Program / Erase Characteristics

(TA = 0 to 70°C or – 40°C to 85°C, VCC=2.7V~3.6V)

Parameter

Symbol

Min.

Typ.

Max.

Unit

Average Program Time

tPROG

(1)

-

250

750

us

Dummy Busy Time for Cache

Program

tCBSY

(2)

-

3

750

us

Number of Partial Program Cycles

in the Same Page

NOP

-

4

Cycle

Block Erase Time

tBERS

-

2

10

ms

Dummy Busy Time for Two-Plane Page

Program

tDBSY

0.5

1

us

Note:

1.

Typical program time is defined as the time within which more than 50% of the whole pages are

programmed at 3.3V VCC and 25°C temperature.

2.

tPROG is the average program time of all pages. Users should be noted that the program time

variation from page to page is possible.

3.

Max. time of tCBSY depends on timing between internal program completion and data in.

AC Timing Characteristics for Command / Address / Data Input

Parameter

Symbol

Min.

Max.

Unit

CLE Setup Time

tCLS

(1)

12

-

ns

CLE Hold Time

tCLH

5

-

ns

CE# Setup Time

tCS

20

-

ns

CE# Hold Time

tCH

5

-

ns

WE# Pulse Width

tWP

12

-

ns

ALE Setup Time

tALS

(1)

12

-

ns

ALE Hold Time

tALH

5

-

ns

Data Setup Time

tDS

(1)

12

-

ns

Data Hold Time

tDH

5

-

ns

Write Cycle Time

tWC

25

-

ns

WE# High Hold Time

tWH

10

-

ns

ALE to Data Loading Time

tADL

(2)

100

(2)

-

ns

Note:

1.

The transition of the corresponding control pins must occur only once while WE# is held low.

2.

tADL is the time from the WE# rising edge of final address cycle to the WE# rising edge of first data

cycle.

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