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R1Q4A4418RBG-33IA0 Datasheet(PDF) 6 Page - Renesas Technology Corp |
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R1Q4A4418RBG-33IA0 Datasheet(HTML) 6 Page - Renesas Technology Corp |
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6 / 31 page  R1Q4A4436RBG, R1Q4A4418RBG Datasheet R10DS0146EJ0102 Rev.1.02 Page 6 of 30 Aug 01, 2014 Pin Descriptions Name I/O type Descriptions Note SAx Input Synchronous address inputs: These inputs are registered and must meet the setup and hold times around the rising edge of K. SA0 is used as the lowest address bit for burst READ and burst WRITE operations permitting a random burst start address on ×18 and ×36 of DDR II devices. These inputs are ignored when device is deselected. /LD Input Synchronous load: This input is brought low when a bus cycle sequence is to be defined. This definition includes address and READ/WRITE direction. R-/W Input Synchronous read / write Input: When /LD is low, this input designates the access type (READ when R-/W is high, WRITE when R-/W is low) for the loaded address. R-/W must meet the setup and hold times around the rising edge of K. /BWx Input Synchronous byte writes: When low, these inputs cause their respective byte to be registered and written during WRITE cycles. These signals are sampled on the same edge as the corresponding data and must meet setup and hold times around the rising edges of K and /K for each of the rising edge comprising the WRITE cycle. See Byte Write Truth Table for signal to data relationship. K, /K Input Input clock: This input clock pair registers address and control inputs on the rising edge of K, and registers data on the rising edge of K and the rising edge of /K. /K is ideally 180 degrees out of phase with K. All synchronous inputs must meet setup and hold times around the clock rising edges. These balls cannot remain VREF level. C, /C Input Output clock: This clock pair provides a user-controlled means of tuning device output data. Ideally, /C is 180 degrees out of phase with C. If C and /C are tied high, K and /K are used as the output reference clocks instead of C and /C clocks. If tied high, C and /C must remain high and not to be toggled during device operation. These balls cannot remain VREF level. /DOFF Input PLL disable: When low, this input causes the PLL to be bypassed for stable, low frequency operation. TMS TDI Input IEEE1149.1 test inputs: 1.8 V I/O levels. These balls may be left unconnected if the JTAG function is not used in the circuit. TCK Input IEEE1149.1 clock input: 1.8 V I/O levels. This ball must be tied to VSS if the JTAG function is not used in the circuit. ZQ Input Output impedance matching input: This input is used to tune the device outputs to the system data bus impedance. Q and CQ output impedance are set to 0.2 × RQ, where RQ is a resistor from this ball to ground. This ball can be connected directly to VDDQ, which enables the minimum impedance mode. This ball cannot be connected directly to VSS or left unconnected. |
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