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R1Q4A4418RBG-40IB0 Datasheet(PDF) 11 Page - Renesas Technology Corp |
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R1Q4A4418RBG-40IB0 Datasheet(HTML) 11 Page - Renesas Technology Corp |
11 / 31 page R1Q4A4436RBG, R1Q4A4418RBG Datasheet R10DS0146EJ0102 Rev.1.02 Page 11 of 30 Aug 01, 2014 K Truth Table Operation K /LD R-/W DQ Write Cycle: Load address, input write data on two consecutive K and /K rising edges ↑ L L Data in Input data D(A+0) D(A+1) Input clock K(t+1) ↑ /K(t+1) ↑ Read Cycle: Load address, output read data on two consecutive C and /C rising edges ↑ L H Data out Output data Q(A+0) Q(A+1) Input clock /C(t+1) ↑ C(t+2) ↑ NOP (No operation) ↑ H x High-Z Standby (Clock stopped) Stopped x x Previous state Notes: 1. H: high level, L: low level, ×: don’t care, ↑: rising edge. 2. Data inputs are registered at K and /K rising edges. Data outputs are delivered at C clock edges, except if C and /C are high, then data outputs are delivered at K clock edges. 3. /LD and R-/W must meet setup/hold times around the rising edges (low to high) of K and are registered at the rising edge of K. 4. This device contains circuitry that will ensure the outputs will be in high-Z during power-up. 5. Refer to state diagram and timing diagrams for clarification. 6. When clocks are stopped, the following cases are recommended; the case of K = low, /K = high, C = low and /C = high, or the case of K = high, /K = low, C = high and /C = low. This condition is not essential, but permits most rapid restart by overcoming transmission line charging symmetrically. 7. A+0 refers to the address input during a WRITE or READ cycle. A+1 refers to the next internal burst address in accordance with the linear burst sequence. Burst Address Table First Address (External) Second Address (Internal) X..X0 X..X1 X..X1 X..X0 |
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