R1QHA4436RBG-25IB0 datasheet(7/30 Pages) RENESAS

Part #	R1QHA4436RBG-25IB0

Description	144-Mbit DDR?줚I SRAM 2-word Burst Architecture (2.0 Cycle Read latency)

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Manufacturer	RENESAS [Renesas Technology Corp]

Direct Link	http://www.renesas.com

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7 / 30 page

R1QHA4436RBG,R1QHA4418RBG

Datasheet

R10DS0145EJ0200 Rev.2.00

Page 7 of 29

Aug 01, 2014

Name

I/O type

Descriptions

Note

DQ0 to DQn

Input

Output

Synchronous data I/Os: Input data must meet setup and hold times around the

rising edges of K and /K. Output data is synchronized to the K clock.

The

×18 device uses DQ0 to DQ17. DQ18 to DQ35 should be treated as NC pin.

The

×36 device uses DQ0 to DQ35.

CQ, /CQ

Output

Synchronous echo clock outputs: The edges of these outputs are tightly matched

to the synchronous data outputs and can be used as a data valid indication.

These signals run freely and do not stop when DQ tri-states.

TDO

Output

IEEE 1149.1 test output: 1.8 V I/O level.

QVLD

Output

Valid output indicator: The Q Valid indicates valid output data. QVLD is edge

aligned with CQ and /CQ.

VDD

Supply

Power supply: 1.8 V nominal. See DC Characteristics and Operating Conditions

for range.

1

VDDQ

Supply

Power supply: Isolated output buffer supply. Nominally 1.5 V. See DC

Characteristics and Operating Conditions for range.

1

VSS

Supply

Power supply: Ground.

1

VREF

-

HSTL input reference voltage: Nominally VDDQ/2, but may be adjusted to improve

system noise margin. Provides a reference voltage for the HSTL input buffers.

NC

-

No connect: These pins can be left floating or connected to 0V to VDDQ.

Notes:

1.

All power supply and ground balls must be connected for proper operation of the device.

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R1QHA4436RBG-25IB0 Datasheet(PDF) 7 Page - Renesas Technology Corp

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