R1QNA4436RBG,R1QNA4418RBG

Datasheet

R10DS0148EJ0200 Rev.2.00

Page 9 of 29

Aug 01, 2014

Status

Power Up &

Unstable Stage

NOP &

Set-up Stage

Normal

Operation

V

DD

SET-UP Cycle

V

DDQ

V

REF

/DOFF

K, /K

Fix High (=Vddq)

Power-up and Initialization Sequence

- Then execute either one of the following sequences.

1. Single Clock Mode

- Drive /DOFF high (/DOFF can be tied high from the start).

- Then provide stable clocks (K, /K) for at least 20 us.

2. PLL Off Mode (/DOFF tied low)

- In the "NOP and setup stage", provide stable clocks (K, /K) for at least 20 us.

PLL Constraints

1.

These chips use the PLL. The clock input should have low phase jitter which is specified as tKC var.

2.

The lower end of the frequency at which the PLL can operate is 250 MHz.

(Please refer to AC Characteristics table for detail.)

3.

When the operating frequency is changed or /DOFF level is changed, setup cycles are required again.