R10DS0244EJ0002 Rev.0.02

Page 1 of 29

Dec. 01, 2014

Preliminary Datasheet

RMQCBA3636DGBA, RMQCBA3618DGBA

36-Mbit DDR™ II+ SRAM 2-word Burst

Architecture (2.5 Cycle Read latency)

Description

The RMQCBA3636DGBA is a 1,048,576-word by 36-bit and the RMQCBA3618DGBA is a 2,097,152-word by 18-bit

synchronous quad data rate static RAM fabricated with advanced CMOS technology using full CMOS six-transistor

memory cell. It integrates unique synchronous peripheral circuitry and a burst counter. All input registers are

controlled by an input clock pair (K and /K) and are latched on the positive edge of K and /K. These products are

suitable for applications which require synchronous operation, high speed, low voltage, high density and wide bit

configuration. These products are packaged in 165-pin plastic FBGA package.

Features

Power Supply

Clock

Fast clock cycle time for high bandwidth

Two input clocks (K and /K) for precise DDR timing at clock rising edges only

Two output echo clocks (CQ and /CQ) simplify data capture in high-speed systems

Clock-stop capability with

μs restart

I/O

Common data input/output bus

Pipelined double data rate operation

HSTL I/O

User programmable output impedance

PLL circuitry for wide output data valid window and future frequency scaling

Data valid pin (QVLD) to indicate valid data on the output

Function

Two-tick burst for low DDR transaction size

Internally self-timed write control

Simple control logic for easy depth expansion

JTAG 1149.1 compatible test access port

Package

165 FBGA package (13 x 15 x 1.4 mm)

R10DS0244EJ0002

Rev.0.02

Dec. 01, 2014