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ISL6244HRZ Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6244HRZ Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 25 page 7 FN9106.3 December 28, 2004 Functional Pin Description ISL6244CR (32 LEAD QFN 5x5) TOP VIEW GND Bias and reference ground for the IC. VFF This pin is connected to VIN through a 10:1 voltage divider to allow for battery “feed-forward,” which improves stability over varying input line. VID4, VID3, VID2, VID1, VID0 The state of these five inputs program the internal DAC, which provides the reference voltage for output regulation. Connect these pins to either open-drain or active pull-up type outputs. Pulling these pins above 2.9V can cause a reference offset inaccuracy. OFS Connecting a resistor between this pin and ground creates a positive offset voltage which is added to the DAC voltage, allowing easy implementation of load-line regulation. For no offset, simply tie this pin to ground. FB and COMP The internal error amplifier inverting input and output respectively. Connect the external R-C feedback compensation network of the regulator to these pins. IOUT The current carried out of this pin is proportional to output current and can be used to incorporate output voltage droop and/or load sharing. The scale factor is set by the ratio of the ISEN resistors and the lower MOSFET rDS(ON). If droop is desired, connect this pin to FB. When not used for droop or load sharing, simply leave this pin open. VSEN, RGND, VDIFF VSEN and RGND are the inputs to the differential remote- sense amplifier. Connect these pins to the sense points of the remote load. Connect an appropriately sized feedback resistor, RFB, between VDIFF and FB. VCC Supplies all the power necessary to operate the chip. The IC starts to operate when the voltage on this pin exceeds the rising POR threshold and shuts down when the voltage on this pin drops below the falling POR threshold. Connect this pin directly to a +5V supply. ISEN1, ISEN2, ISEN3, ISEN4 Current sense inputs. A resistor connected between these pins and their respective phase node sets a current proportional to the current in the lower MOSFET during it’s conduction interval. This current is used as a reference for channel balancing, load sharing, protection, and load-line regulation. Inactive channels should have their respective sense inputs left open. PWM1, PWM2, PWM3, PWM4 Pulse-width modulating outputs. Connect these pins to the individual ISL620X driver PWM input pins. These logic outputs command the driver IC(s) in switching the half- bridge configuration of MOSFETs. The number of active channels is determined by the state of PWM3 and PWM4. If PWM3 is tied to VCC, this indicates to the controller that two channel operation is desired. In this case, PWM 4 should be left open or tied to VCC. Shorting PWM4 to VCC indicates that three channel operation is desired. PGOOD Power good is an open-drain logic output that changes to a logic low when the voltage at VDIFF is 350mV below the VID setting (under-voltage) or above 2.2V (over-voltage). FS A pin for setting the switching frequency of the regulator. Place a resistor from this pin to ground to set the switching frequency between 80kHz and 1MHz. EN This pin enables the ISL6244 regulator. 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 9 1011 12 13 1415 16 VID2 VID1 VID0 NC OFS COMP FB NC ISEN3 ISEN2 GND PWM2 PWM1 ISEN1 ISEN4 PWM4 NC = NO CONNECT ISL6244 |
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