7

Functional Description

The ISL6405 dual output voltage regulator makes an ideal

choice for advanced satellite set-top box and personal video

recorder applications. Both supply and control voltage

outputs for two low-noise blocks (LNBs) are available

simultaneously in any output configuration. The device

utilizes built-in DC/DC step-converters that, from a single

supply source ranging from 8V to 14V, generate the voltages

that enable the linear post-regulators to work with a

minimum of dissipated power. An undervoltage lockout

circuit disables the circuit when VCC drops below a fixed

threshold (7.5V typ).

DiSEqC Encoding

The internal oscillator is factory-trimmed to provide a tone

of 22kHz in accordance with DiSEqC (EUTELSAT)

standards. No further adjustment is required. The 22kHz

(ENT1/2 bit) or by a dedicated pin (DSQIN1/2) that allows

immediate DiSEqC data encoding separately for each LNB.

(Please see Note 1 at the end of this section.) All the

to the system registers (SR1, SR2). The same registers

can be read back, and two bits will report the diagnostic

status. The internal oscillator operates the converters at ten

compatible functionality, 3.3V or 5V, and up to 400kHz

operation.

the DSQIN1/2 terminal activates the internal tone signal,

modulating the dc output with a 0.3V, 22kHz, symmetrical

waveform. The presence of this signal usually gives the LNB

information about the band to be received.

Burst coding of the 22kHz tone can be accomplished due to

the fast response of the DSQIN1/2 input and rapid tone

response. This allows implementation of the DiSEqC

(EUTELSAT) protocols.

When the ENT1/2 bit is set HIGH, a continuous 22kHz tone

is generated regardless of the DSQIN1/2 pin logic status for

the corresponding regulator channel (LNB-A or LNB-B). The

ENT1/2 bit must be set LOW when the DSQIN1 and/or

DSQIN2 pin is used for DiSEqC encoding.

Linear Regulator

The output linear regulator will sink and source current. This

feature allows full modulation capability into capacitive loads

as high as 0.25

µF. In order to minimize the power

dissipation, the output voltage of the internal step-up

converter is adjusted to allow the linear regulator to work at

minimum dropout.

When the device is put in the shutdown mode (EN1,

EN2 = LOW), both PWM power blocks are disabled. (i.e.

when EN1 = 0, PWM1 is disabled, and when EN2 = 0,

PWM2 is disabled).

When the regulator blocks are active (EN1, EN2 = HIGH),

the output can be logic controlled to be 13V or 18V (typical)

by mean of the VSEL bit (Voltage Select) for remote

controlling of non-DiSEqC LNBs. Additionally, it is possible

to increment by 1V (typical) the selected voltage value to

compensate for the excess voltage drop along the coaxial

cable (LLC1/2 bit HIGH).

Output Timing

The programmed output voltage rise and fall times can be

set by an external capacitor. The output rise and fall times

will be approximately 3400 times the TCAP value. For the

recommended range of 0.47

µF to 2.2µF, the rise and fall

time would be 1.6ms to 7.6ms. Using a 0.47

µF capacitor

insures the PWM stays below its overcurrent threshold when

charging a 120

µF VSW filter cap during the worst case 13V

to 19V transition. A typical value of 1.0

µF is recommended.

Functional Pin Description

SYMBOL

FUNCTION

SDA

SCL

VSW1, 2

Input of the linear post-regulator.

PGND1, 2

Dedicated ground for the output gate driver of

respective PWM.

CS1, 2

Current sense input; connect Rsc at this pin for

desired over current value for respective PWM.

SGND

Small signal ground for the IC.

AGND

Analog ground for the IC.

TCAP1, 2

Capacitor for setting rise and fall time of the output

of LNB A and LNB B respectively. Use this

capacitor value 1µF or higher.

BYPASS

Bypass capacitor for internal 5V.

DSQIN1, 2

When HIGH enables internal 22kHz modulation for

LNB A and LNA B respectively, Use this pin for

tone enable function for LNB A and LNB B.

VCC

Main power supply to the chip.

GATE1, 2

These are the device outputs of PWM A and

PWM B respectively. These high current driver

outputs are capable of driving the gate of a power

FET. These outputs are actively held low when

Vcc is below the UVLO threshold.

VO1, 2

Output voltage of LNB A and LNB B respectively.

ADDR

Address pin to select two different addresses per

voltage level at this pin.

COMP1, 2

Error amp outputs used for compensation.

FB1, 2

Feedback pins for respective PWMs

CPVOUT,

CPSWIN,

CPSWOUT

Charge pump connections.

SEL18V1, 2

When connected HIGH, this pin will change the

output of the respective PWM to 18V. Only

available on the QFN package option.

ISL6405