8

This feature only affects the turn-on and programmed

voltage rise and fall times.

Current Limiting

The current limiting block has two thresholds that can be

selected by the ISEL bit of the SR and can work either

statically (simple current clamp) or dynamically. The lower

threshold is between 425mA and 530mA (ISEL = L), while

the higher threshold is between 775mA and 925mA

(ISEL = H). When the DCL (Dynamic Current Limiting) bit is

set to LOW, the over current protection circuit works

dynamically: as soon as an overload is detected, the output

the OLF bit of the System Register is set to HIGH. After this

425mA or 775mA, depending on the ISEL bits. At the end of

which no overload is detected, normal operation is resumed

920ms as determined by an internal timer. This dynamic

operation can greatly reduce the power dissipation in a short

circuit condition, still ensuring excellent power-on start-up in

most conditions.

However, there could be some cases in which a highly

capacitive load on the output may cause a difficult start-up

when the dynamic protection is chosen. This can be solved

by initiating any power start-up in static mode (DCL = HIGH)

and then switching to the dynamic mode (DCL = LOW) after

a chosen amount of time. When in static mode, the OLF1/2

bit goes HIGH when the current clamp limit is reached and

returns LOW when the overload condition is cleared. The

OLF1/2 bit will be LOW at the end of initial power-on soft-start.

Thermal Protection

This IC is protected against overheating. When the junction

temperature exceeds 150°C (typical), the step-up converter

and the linear regulator are shut off and the OTF bit of the

SR is set HIGH. Normal operation is resumed and the OTF

bit is reset LOW when the junction is cooled down to 135°C

(typical).

In over temperature conditions, the OTF Flag goes HIGH

also make the OLF flags go HIGH, when high capacitive

loads are present or self-heating conditions occur at higher

loads.

External Output Voltage Selection

Additionally, the QFN package offers two pins (SEL18V1,

SEL18V2) for independent 13V/18V output voltage

initialized to 13V status.

Data transmission from main microprocessor to the ISL6405

interface, consisting of the two lines SDA and SCL. Both SDA

and SCL are bidirectional lines, connected to a positive supply

voltage via a pull up resistor. (Pull up resistors to positive supply

voltage must be externally connected). When the bus is free,

both lines are HIGH. The output stages of ISL6405 will have an

open drain/open collector in order to perform the wired-AND

in the standard-mode or up to 400Kbps in the fast-mode. The

level of logic “0” and logic “1” is dependent of associated value

generated for each data bit transferred.

Data Validity

The data on the SDA line must be stable during the HIGH

period of the clock. The HIGH or LOW state of the data line

can only change when the clock signal on the SCL line is

LOW. Refer to Figure 1.

START and STOP Conditions

As shown in Figure 2, START condition is a HIGH to LOW

transition of the SDA line while SCL is HIGH.

The STOP condition is a LOW to HIGH transition on the SDA

line while SCL is HIGH. A STOP condition must be sent

before each START condition.

TABLE 1.

SEL18V (1, 2)

O/P VOLTAGE

13V

Low

13V

14V

Low

14V

13V

High

18V

14V

High

19V

SDA

SCL

DATA LINE

STABLE

DATA VALID

CHANGE

OF DATA

ALLOWED

FIGURE 1. DATA VALIDITY

SDA

SCL

START

CONDITION

FIGURE 2. START AND STOP WAVEFORMS

STOP

CONDITION

SP

ISL6405