9

The ISL6421 can provide to the master a copy of the System

mode is Master activated by sending the chip address with

R/W bit set to 1. At the following Master generated clock bits,

the ISL6421 issues a byte on the SDA data bus line (MSB

transmitted first).

At the ninth clock bit the MCU master can:

• Acknowledge the reception, starting in this way the

transmission of another byte from the ISL6421.

• Not acknowledge, stopping the read mode

communication.

While the whole register is read back by the microprocessor,

only the two read-only bits, OLF and OTF, convey diagnostic

information about the ISL6421.

logic signal from the UVLO circuit. This signal will go HIGH

when chip power is OK. As long as this signal is LOW, the

system register SR is initialized to all zeros, thus keeping the

power blocks disabled.

Once Vcc rises above the UVLO level, the POWER OK

interface becomes operative and the SR can be configured

by the main microprocessor. About 400mV of hysteresis is

provided in the UVLO threshold to avoid false triggering of

the Power-On reset circuit.

valid).

ADDRESS Pin

address to 0001000; applying a voltage >2.7V forces the

address to 0001001, as shown below.

0

1

1

1

Dynamic current limit NOT selected

0

0

1

1

Dynamic current limit selected

0

X

1

X

X

X

0

PWM and Linear for channel 1 disabled

TABLE 5. SYSTEM REGISTER (SR1 AND SR2) CONFIGURATION (Continued)

SR

DCL

ISEL1

ENT1

LLC1

VSEL1

EN1

OLF1

FUNCTION

SR

----

EN2

OTF

-

FUNCTION

1

X

X

X

X

0

X

X

SR2 is selected; to read OTF flag.

TABLE 6. READING SYSTEM REGISTERS

DCL ISEL ENT LLC VSEL EN OTF OLF

FUNCTION

These bits are read as they were

after the last write operation.

0

Tj <= 130°C, Normal

operation

1

Tj > 150°C, Power

blocks disabled

0

Iout < Imax, Normal

operation

1

Iout > Imax, Overload

protection triggered

TABLE 7. ADDRESS PIN CHARACTERISTICS

VADDR

MIN

TYP

MAX

Vaddr-1

“0001000”

0V

-

2.0V

Vaddr-2

“0001001”

2.7V

-

5.0V

PARAMETER

TEST

CONDITION

MIN

TYP

MAX

Input Logic High,

VIH

SDA, SCL

Input Logic Low,

VIL

SDA, SCL

Input Logic

Current, IIL

SDA, SCL;

0.4V < Vin < 4.5V

10

µA

SCL Clock

Frequency

0

100kHz

400kHz

ISL6421