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ISL6520CBZ-T Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL6520CBZ-T Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 11 page 6 FN9009.4 October 4, 2005 Please note that the capacitors CIN and CO may each represent numerous physical capacitors. Locate the ISL6520 within 3 inches of the MOSFETs, Q1 and Q2. The circuit traces for the MOSFETs’ gate and source connections from the ISL6520 must be sized to handle up to 1A peak current. Figure 4 shows the circuit traces that require additional layout consideration. Use single point and ground plane construction for the circuits shown. Minimize any leakage current paths on the COMP/OCSET pin and locate the resistor, ROSCET close to the COMP/OCSET pin because the internal current source is only 20 µA. Provide local VCC decoupling between VCC and GND pins. Locate the capacitor, CBOOT as close as practical to the BOOT and PHASE pins. All components used for feedback compensation should be located as close to the IC a practical. Feedback Compensation Figure 5 highlights the voltage-mode control loop for a synchronous-rectified buck converter. The output voltage (VOUT) is regulated to the Reference voltage level. The error amplifier (Error Amp) output (VE/A) is compared with the oscillator (OSC) triangular wave to provide a pulse- width modulated (PWM) wave with an amplitude of VIN at the PHASE node. The PWM wave is smoothed by the output filter (LO and CO). Modulator Break Frequency Equations The compensation network consists of the error amplifier (internal to the ISL6520) and the impedance networks ZIN and ZFB. The goal of the compensation network is to provide a closed loop transfer function with the highest 0dB crossing frequency (f0dB) and adequate phase margin. Phase margin is the difference between the closed loop phase at f0dB and 180 degrees. The equations below relate the compensation network’s poles, zeros and gain to the components (R1, R2, R3, C1, C2, and C3) in Figure 7. Use these guidelines for locating the poles and zeros of the compensation network: 1. Pick Gain (R2/R1) for desired converter bandwidth. 2. Place 1ST Zero Below Filter’s Double Pole (~75% FLC). 3. Place 2ND Zero at Filter’s Double Pole. 4. Place 1ST Pole at the ESR Zero. 5. Place 2ND Pole at Half the Switching Frequency. 6. Check Gain against Error Amplifier’s Open-Loop Gain. 7. Estimate Phase Margin - Repeat if Necessary. The modulator transfer function is the small-signal transfer function of VOUT/VE/A. This function is dominated by a DC Gain and the output filter (LO and CO), with a double pole break frequency at FLC and a zero at FESR. The DC Gain of the modulator is simply the input voltage (VIN) divided by the peak-to-peak oscillator voltage ∆VOSC. Compensation Break Frequency Equations Figure 6 shows an asymptotic plot of the DC/DC converter’s gain vs frequency. The actual Modulator Gain has a high gain peak due to the high Q factor of the output filter and is not shown in Figure 6. Using the above guidelines should give a Compensation Gain similar to the curve plotted. The open loop error amplifier gain bounds the compensation gain. FIGURE 4. PRINTED CIRCUIT BOARD SMALL SIGNAL LAYOUT GUIDELINES +5V ISL6520 COMP/OCSET GND VCC BOOT D1 LO CO VOUT Q1 Q2 PHASE +VIN CBOOT CVCC +5V FLC 1 2 π x LO x CO ------------------------------------------- = FESR 1 2 π x ESR x CO -------------------------------------------- = FIGURE 5. VOLTAGE-MODE BUCK CONVERTER COMPENSATION DESIGN VOUT REFERENCE LO CO ESR VIN ∆VOSC ERROR AMP PWM DRIVER (PARASITIC) ZFB + - REFERENCE R1 R3 R2 C3 C2 C1 COMP VOUT FB ZFB ISL6520 ZIN COMPARATOR DRIVER DETAILED COMPENSATION COMPONENTS PHASE VE/A + - + - ZIN OSC FZ1 1 2 π x R 2 x C1 ------------------------------------ = FZ2 1 2 π x R 1 R3 + () x C 3 ------------------------------------------------------- = FP1 1 2 π x R 2 x C1 x C2 C1 C2 + ---------------------- --------------------------------------------------------- = FP2 1 2 π x R 3 x C3 ------------------------------------ = ISL6520 |
Similar Part No. - ISL6520CBZ-T |
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Similar Description - ISL6520CBZ-T |
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