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ISL6530CB Datasheet(PDF) 6 Page - Intersil Corporation |
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ISL6530CB Datasheet(HTML) 6 Page - Intersil Corporation |
6 / 17 page 6 FN9052.2 November 15, 2004 Functional Pin Description 24 LEAD (SOIC) TOP VIEW 32 LEAD (QFN) TOP VIEW BOOT1 and BOOT2 These pins provide bias voltage to the upper MOSFET drivers. A single capacitor bootstrap circuit may be used to create a BOOT voltage suitable to drive a standard N- Channel MOSFET. UGATE1 and UGATE2 Connect UGATE1 and UGATE2 to the corresponding upper MOSFET gate. These pins provide the gate drive for the upper MOSFETs. UGATE2 is also monitored by the adaptive shoot through protection to determine when the upper FET of the VTT regulator has turned off. LGATE1 and LGATE2 Connect LGATE1 and LGATE2 to the corresponding lower MOSFET gate. These pins provide the gate drive for the lower MOSFETs. These pins are monitored by the adaptive shoot through protection to determine when the lower FET has turned off. PGND1 and PGND2 These are the power ground connections for the gate drivers of the PWM controllers. Tie these pins to the ground plane through the lowest impedence connection available. OCSET/SD A resistor (ROCSET) connected from this pin to the drain of the upper MOSFET of the VDDQ regulator sets the overcurrent trip point. ROCSET, an internal 40µA current source (IOCS), and the upper MOSFET on-resistance (rDS(ON)) set the VDDQ converter over-current (OC) trip point according to the following equation: An overcurrent trip cycles the soft-start function. Pulling the OCSET/SD pin to ground resets the ISL6530 and all external MOSFETS are turned off allowing the two output voltage power rails to float. PGOOD A high level on this open-drain output indicates that both the VDDQ and VTT regulators are within normal operating voltage ranges. GNDA Signal ground for the IC. Tie this pin to the ground plane through the lowest impedence connection available. VCC The 5V bias supply for the chip is connected to this pin. This pin is also the positive supply for the lower gate driver, LGATE2. Connect a well decoupled 5V supply to this pin. V2_SD A high level on the V2_SD input places the V2 controller into “sleep” mode. In sleep mode, both UGATE2 and LGATE2 are driven low, effectively floating the VTT supply. 15 16 17 10 9 8 VREF_IN PHASE2 SENSE2 FB2 VCC GNDA 18 19 20 21 22 23 24 7 6 5 4 3 2 1 BOOT1 PHASE1 FB1 SENSE1 VREF PGND1 PVCC1 OCSET/SD V2_SD PGOOD COMP2 LGATE1 COMP1 UGATE1 13 14 12 11 UGATE2 LGATE2 PGND2 BOOT2 PHASE 1 VREF FB1 COMP1 SENSE1 VREF_IN GNDA GNDA PVCC1 OCSET/SD V2_SD PGOOD COMP2 SENSE2 FB2 VCC 1 2 3 4 5 6 7 8 24 23 22 21 20 19 18 17 32 31 30 29 28 27 26 25 910 11 12 13 14 15 16 I PEAK I OCS R OCSET • r DS ON () -------------------------------------------- = ISL6530 |
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