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ADSP-2141L Datasheet(PDF) 11 Page - Analog Devices

Part # ADSP-2141L
Description  highly integrated embedded security processor that incorporates a sophisticated
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Manufacturer  AD [Analog Devices]
Direct Link  http://www.analog.com
Logo AD - Analog Devices

ADSP-2141L Datasheet(HTML) 11 Page - Analog Devices

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ADSP-2141L
–11–
IDMA Mode Multiplex Bus Pin Definition
IDMA Port (218x Mode)
PIN FUNCTION DESCRIPTIONS—IDMA Mode Multiplex Bus
Pin Name
IDMA Name
Pins
I/O
Description
MPLX5
IRD
1
I
IDMA Port Read Input
MPLX6
IWR
1
I
IDMA Port Write Input
MPLX7
IS
1
I
IDMA Port Select
MPLX8
IAL
1
I
IDMA Port Address Latch
MPLX9
IACK
1
O
IDMA Port Access Ready Acknowledge
MPLX10
FL0
1
O
Output Flags
MPLX11
FL1
1
O
Output Flags
MPLX12
FL2
1
O
Output Flags
MPLX_BUS
IAD
16
I/O
IDMA Data I/O
PCI Port
PIN FUNCTION DESCRIPTIONS—PCI Mode Multiplex Bus
Pin Name
PCI Name
Pins
I/O
Description
MPLX1
Pci_
cbe3
1
I/O
Bus Command / Byte Enable 3
MPLX2
Pci_
cbe2
1
I/O
Bus Command / Byte Enable 2
MPLX3
Pci_
cbe1
1
I/O
Bus Command / Byte Enable 1
MPLX4
Pci_
cbe0
1
I/O
Bus Command / Byte Enable 0
MPLX5
Pci_idsel
1
I
Initialization Device Select
MPLX6
Pci_
gnt
1
I
Bus Grant
MPLX7
Pci_
frame
1
I/O
Cycle Frame
MPLX8
Pci_
devsel
1
I/O
Device Select
MPLX9
Pci_
trdy
1
I/O
Target Ready
MPLX10
Pci_
perr
1
I/O
Parity Error
MPLX11
Pci_
serr
1
I/O
System Error
MPLX12
Pci_
req
1
O
PCI Bus Request
MPLX_BUS
Pci_ad15:0
Pci_ad31:16
32
I/O
PCI Address/Data Bus
PF7/
INT_H
Pci_
intA
1
O
PCI Interrupt A Request
SYSTEM INTERFACE
The ADSP-2141L may be integrated into a wide variety of sys-
tems, including those that already have a microprocessor and
those that will use the ADSP-2141L as the main processor. The
device can be configured into one of two Host Bus modes:
IDMA or PCI.
IDMA Bus Mode
The IDMA bus mode operates the same as in a native ADSP-
218x device, as described in this section.
The IDMA port provides an efficient means of communication
between a host system and the ADSP-2141L. The port is used
to access the on-chip program memory and data memory of the
DSP with only one DSP cycle per word overhead. The IDMA
port cannot, however, be used to write to the DSP’s memory-
mapped control registers.
The IDMA port has a 16-bit multiplexed address and data bus,
and supports reading or writing 16-bit data (DM) or 24-bit
program memory (PM). The IDMA port is completely asyn-
chronous and can be written to while the ADSP-2141L is oper-
ating at full speed.
The DSP memory address is latched and then automatically
incremented after each IDMA transaction. An external device can
therefore access a block of sequentially addressed memory by
specifying only the starting address of the block. This increases
throughput as the address does not have to be sent for each
memory access.
The IDMA port access occurs in two phases. The first is the
IDMA address latch cycle. When the acknowledge is asserted, a
14-bit address and 1-bit destination type can be driven onto the
bus by an external device. The address specifies an on-chip
memory location; the destination type specifies whether it is a
DM or PM access. The falling edge of the address latch signal
latches this value to the IDMAA register.
Once the address is stored, data can either be read from or
written to the ADSP-2141L’s on-chip memory. Asserting the
select line (
IS) and the appropriate read or write line (IRD and
IWR respectively) signals the ADSP-2141L that a particular
transaction is required. In either case, there is a one-processor-
cycle delay for synchronization. The memory access consumes
an additional processor cycle.
Once an access has occurred, the latched address is automati-
cally incremented and another access can occur.
Through the IDMAA register, the ADSP-2141L can also
specify the starting address and data format for DMA operation.
Figure 6 illustrates a typical system configuration for the
IDMA mode.


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