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FN9052.2

November 15, 2004

via the SENSE2 pin. The window regulator can overcome up

to at least

While V2_SD is high, PGOOD is low.

PHASE1 and PHASE2

Connect PHASE1 and PHASE2 to the corresponding upper

MOSFET source. This pin is used as part of the upper

MOSFET bootstrapped drives. PHASE1 is used to monitor

regulator for over-current protection. The PHASE1 pin is

monitored by the adaptive shoot through protection circuitry

turned off.

FB1, COMP1, FB2, and COMP2

COMP1, COMP2, FB1, and FB2 are the available external

pins of the error amplifiers. The FB1 and FB2 pins are the

inverting inputs of each error amplifier and the COMP1 and

COMP2 pins are the associated outputs. An appropriate AC

network across these pins is used to compensate the

voltage-controlled feedback loop of each converter.

VREF and VREF_IN

VREF produces a voltage equal to one half of the voltage on

SENSE1. This low current output is connected to the VREF

input of the DDRAM devices being powered. This same

VREF_IN is used as an option to overdrive the internal

resistor divider network that sets the voltage for both

100pF capacitor between VREF_IN and ground is

recommended for proper operation.

PVCC1

This is the positive supply for the lower gate driver, LGATE1.

PVCC1 is connected to a well decoupled 5V.

SENSE1 and SENSE2

Both SENSE1 and SENSE2 are connected directly to the

respectively. SENSE1 is used as an input to create the

supply. SENSE2 is used as the regulation point for the

window regulator that is enabled in V2_SD mode.

Functional Description

Overview

The ISL6530 contains control and drive circuitry for two

synchronous buck PWM voltage regulators. Both regulators

utilize 5V bootstrapped output topology to allow use of low

cost N-channel MOSFETs. The regulators are driven by

300kHz clocks. The clocks are phase locked and displaced

The first regulator includes a precision 0.8V reference and is

via a digital softstart circuit.

is derived via a precision internal resistor divider connected

to the SENSE1 terminal.

termination for the DDRAM signal lines. The reference to the

Two benefits result from the ISL6530 dual controller

Initialization

The ISL6530 automatically initializes upon application of

input power. Special sequencing of the input supplies is not

necessary. The Power-On Reset (POR) function continually

monitors the input bias supply voltage at the VCC pin. The

POR function initiates soft-start operation after the 5V bias

supply voltage exceeds its POR threshold.

Soft-Start

The POR function initiates the digital soft start sequence. The

PWM error amplifier reference input for the VDDQ regulator is

clamped to a level proportional to the soft-start voltage. As the

soft-start voltage slews up, the PWM comparator generates

PHASE pulses of increasing width that charge the output

capacitor(s). This method provides a rapid and controlled

output voltage rise. The soft start sequence typically takes

about 7ms.

it will

Figure 2 shows the soft-start sequence for a typical application.

At t0, the +5V VCC bias voltage starts to ramp. Once the

voltage on VCC crosses the POR threshold at time t1, both

outputs begin their soft-start sequence. The triangle waveforms

from the PWM oscillators are compared to the rising error

amplifier output voltage. As the error amplifier voltage

increases, the pulse-widths on the UGATE pins increase to

reach their steady-state duty cycle at time t2.

1

2

--- V

DDQ

⋅

ISL6530