9

FN9003.3

February 11, 2005

Note that Figure 5 shows the 12V gate driver voltage

available before the 5V supply to the ISL6554 has reached

its threshold level. If conditions were reversed and the 5V

supply was to rise first, the start-up sequence would be

different. In this case the ISL6554 will sense an overcurrent

condition due to charging the output capacitors. The supply

will then restart and go through the normal soft-start cycle.

Fault Protection

The ISL6554 protects the microprocessor and the entire

power system from damaging stress levels. Within the

ISL6554 both Overvoltage and Overcurrent circuits are

incorporated to protect the load and regulator.

Overvoltage

The VSEN pin is connected to the microprocessor CORE

voltage. A CORE overvoltage condition is detected when the

VSEN pin goes more than 15% above the programmed VID

level.

The overvoltage condition is latched, disabling normal PWM

operation, and causing PGOOD to go low. The latch can

only be reset by lowering and returning VCC high to initiate a

POR and soft-start sequence.

During a latched overvoltage, the PWM outputs will be driven

either low or three state, depending upon the VSEN input.

PWM outputs are driven low when the VSEN pin detects that

the CORE voltage is 15% above the programmed VID level.

This condition drives the PWM outputs low, resulting in the

lower or synchronous rectifier MOSFETs to conduct and shunt

the CORE voltage to ground to protect the load.

If after this event, the CORE voltage falls below the over-

voltage limit (plus some hysteresis), the PWM outputs will

three state. The HIP6601 family drivers pass the three-state

information along, and shuts off both upper and lower

MOSFETs. This prevents “dumping” of the output capacitors

back through the lower MOSFETs, avoiding a possibly

destructive ringing of the capacitors and output inductors. If

the conditions that caused the overvoltage still persist, the

clamped to ground, as a hysteretic shunt regulator.

Undervoltage

The VSEN pin also detects when the CORE voltage falls

more than 9% below the VID programmed level. This causes

PGOOD to go low, but has no other effect on operation and

is not latched. There is also hysteresis in this detection point.

Overcurrent

In the event of an overcurrent condition, the overcurrent

protection circuit reduces the RMS current delivered to 41%

of the current limit. When an overcurrent condition is

detected, the controller forces all PWM outputs into a three

state mode. This condition results in the gate driver

removing drive to the output stages. The ISL6554 goes into

a wait delay timing cycle that is equal to the soft-start ramp

PWM 1

PGOOD

5V

OUTPUT

VCC

DELAY TIME

FIGURE 3. START-UP OF 4 PHASE SYSTEM OPERATING AT

500kHz

PGOOD

5V

V COMP

VCC

DELAY TIME

FIGURE 4. START-UP OF 4 PHASE SYSTEM OPERATING AT

200kHz

12V ATX

SUPPLY

PGOOD

5 V ATX

SUPPLY

ATX SUPPLY ACTIVATED BY ATX “PS-ON PIN”

FIGURE 5. SUPPLY POWERED BY ATX SUPPLY

FREQUENCY 200kHz

ISL6554