7

FN9011.3

moves from approximately 1V to 3V, the current comparator

threshold voltage ranges from 0mV to 157mV. Also observe

as the output load demand increases, driving the inverting

input of the error amplifier lower, the output voltage of the

increases the current comparator threshold voltage to satisfy

load demand.

Droop Voltage

is 2.2mS, the gain will be 2.2mS x 10k = 22. For example,

assume to satisfy the no-load to full load requirements the

input voltage or droop voltage will be 1.5V / 22 = 68mV

below the DAC voltage. As will be shown later this is not the

sequence one uses when designing a supply, but is useful at

this point, to explain the operation.

Initial Voltage

The initial starting, or no-load voltage is set by the

programmed DAC voltage and the reference voltage set at

the output of the gm amplifier. The reference voltage is

shown in Figure 1. Assume that the voltage to the current

comparator is set to 1.2V to satisfy the inductor no-load

ripple current. This means that the gm amplifier does not

have to supply any output current. Under this condition, the

error amplifier input is the DAC voltage.

Now assume that the reference voltage to the gm amplifier is

set to 1.4V, instead of 1.2V. The gm amplifier must reduce its

output to 1.2V to set the comparator no-load threshold

voltage to the correct voltage to supply the inductor ripple

current. The error amplifier output must pull down or reduce

the voltage to the comparator by the added 200mV. This will

cause the gm amplifier input to go more positive to drive the

error amplifier output low. The initial no-load voltage, with a

gain of 22, will be 200mV/22 or 9mV high. If the reference

voltage is set low by the same amount the no-load starting

voltage will be low by that same amount.

A 3V reference is provided within the ISL6560. A voltage

divider is established by two external series resistors

connected between the reference voltage, REF and ground.

The center of the two resistors is connected to COMP and

sets the initial voltage. The parallel combination sets the

resistor values will be discussed later.

Oscillator Frequency

An external capacitor establishes the basic timing for the

sawtooth oscillator. An internal current source of 150

µA

ramps the timing capacitor from ground to approximately 3V

with low values of timing capacitors, (< 150pF). This

establishes the basic period for the oscillator. Approximately

150ns is fixed for the retrace. With increasing values of

timing capacitors the sawtooth amplitude is reduced

because the timing capacitor does not retrace to ground.

Figure 3 is a plot of the oscillator frequency versus timing

capacitor value.

During supply start-up, or when the error amplifier input is at

zero volts, the oscillator’s charging current is reduced from

its operating value of 150

µA to 36µA, reducing its frequency.

Monitoring and Protection Systems

Power Good

Internal monitoring circuits verify, via a high open drain

PWRGD output signal, that the supply voltage is within

+124% to -82% of the programed DAC voltage. An external

pull-up resistor must be connected from this pin to a positive

supply. Load currents should be kept below 100

µA. Voltages

exceeding the above limits will drive the open drain PWRGD

pin low.

If the output voltage exceeds the 124% limit, the PWM

outputs will go low, turning OFF the upper gates and turning

ON the lower gates to protect the processor. When the

output voltage drops below the limit, normal operation is

restored.

Short Circuit Protection

When a short is placed on the supply, the input supply

current exceeds the current comparator maximum level. No

more current is available and the output voltage will fall.

When the regulator output voltage falls below approximately

375mv, the threshold voltage of the current comparator is

limited to 95mV. In addition, the oscillator frequency is

reduced. This effectively folds back the available output

current to limit load and regulator dissipation.

Supply Disable

The bracketed section on the left hand vertical axis of the

curve in of Figure 2 shows a range of voltages that will

initiate the disable function within the ISL6560. The PWM

outputs are driven low, opening the upper MOSFETs and

driving the lower MOSFETs ON. The oscillator is disabled

during this time. Connecting an open drain or open collector

disable function.

1000

100

3000

CAPACITOR CT (pF)

100 150 200

250 300

0

50

350 400

450 500

FIGURE 3. OSCILLATOR FREQUENCY vs. TIMING CAPACITOR

ISL6560