5

33

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW

34

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW

35

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW

36

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW

37

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW

38

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high and no fault condition, VCC is switched to VSW

39

GND

I

GND

IC ground

40

ISENSE

MINUS/

GND

I

GND

Ground pin for current sense resistor

41

ISENSE

PLUS

I/O

ANALOG

Low voltage analog output; current representing 1/9900 of the high side PFET current

42

SOC

O

3.3V CMOS

Digital outupt; start of conversion signal (SOC). This signal frames the error word generated by the

voltage A/D when configured in regulation mode.

43

GND

I

GND

IC ground

44

IDIG

O

3.3V CMOS

Digital output; 7 bit serial word transmitted typically at 66.67MHz. The first bit is a start bit (start=1).

This signal represents the sampled peak current in the high side PFET, MSB first

45

VDD

I

VDD

Power supply for the logic typically set at 3.3V

46

VREF

I

VREF

Low voltage analog input; 2.5V reference signal used by the A/D converter and the thermal shutdown

circuits

47

GND

I

GND

IC ground

48

CLK

I

3.3V CMOS

Digital input; typically a 133MHz clock supplied to the Intersil ISL6590

49

ERR

O

3.3V CMOS

Digital output; Voltage A/D output word indicating the error from the desired output voltage and

VSENP-VSENN measured voltage (Output voltage-VID). The error signal is a 6 bit serial word (MSB

first) transmitted typically at 66.67MHz.

50

ATRL

O

3.3V CMOS

Digital output; Active Transient Response Low (ATRL). ATRL indicates the regulated output voltage

has"spiked" above the programmed level.

51

ATRH

O

3.3V CMOS

Digital output; Active Transient Response High (ATRH). ATRH indicates the regulated output voltage

has"drooped" below the programmed level.

52

GND

I

GND

IC ground

53

VSENN

I

LV ANALOG Low voltage analog input; negative input for the remote sense used to differentially sense the

regulated output voltage. The IC is configurable for thre modes of operation: Regulation mode, ATR

mode, and output OV/UV mode

54

VSENP

I

LV ANALOG Low voltage analog input; positive input for the remote sense used to differentially sense the regulated

output voltage. The IC is configurable for thre modes of operation: Regulation mode, ATR mode, and

output OV/UV mode

55

VDD

I

VDD

Power supply for the logic typically set at 3.3V

56

SCLK

I

3.3V CMOS

Digital input; typically 16.67MHz clock supplied by the Intersil ISL6590 digital controller for the

controller interface bus Paddle

PADDLE

VCC

I

VCC

Power supply input typically set at 12V. Provides gate drive and source connection for the integrated

high side PFET

Side Bar

1

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high, VCC is switched to VSW

Side Bar

2

VSW

O

HV ANALOG Drain of high side PFET. When the PWM signal is high, VCC is switched to VSW

PIN #

NAME

I/O

TYPE

DESCRIPTION

ISL6580