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ISL6605CBZ Datasheet(PDF) 7 Page - Intersil Corporation |
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ISL6605CBZ Datasheet(HTML) 7 Page - Intersil Corporation |
7 / 9 page 7 FN9091.5 January 4, 2005 Application Information Fault Mode at Repetitive Startups At a low VCC (<2V), the Thevenin equivalent of the 20k divider at the PWM pin, as shown in the Block Diagram on page 2, is no longer true; very high impedance will be seen from the PWM pin to GND. Junction leakage currents from the VCC to the resistor tub will tend to pull up the PWM input and falsely trigger the UGATE. If the energy stored in the bootstrap capacitor is not completely discharged during the previous power-down period, then the upper MOSFET could be turned on and generate a spike at the output when VCC ramps up. A 499k Ω resistor at the PWM to GND, as shown in Figure 3, helps bleed the leakage currents, thus eliminating the startup spike. Layout Considerations and MOSFET Selection The parasitic inductances of the PCB and the power devices (both upper and lower FETs) generate a negative ringing at the trailing edge of the PHASE node. This negative ringing plus the VCC adds charges to the bootstrap capacitor through the internal bootstrap schottky diode when the PHASE node is low. If the negative spikes are too large, especially at high current applications with a poor layout, the voltage on the bootstrap capacitor could exceed the VCC and the device’s maximum rating. The VBOOT-PHASE voltage should be checked at the worst case (maximum VCC and prior to overcurrent trip point), especially for applications with higher than 20A per D2PAK FET. MOSFETs with low parasitic lead inductances, such as multi-SOURCE leads devices (SO-8 and LFPAK), are recommended. Careful layout would help reduce the negative ringing peak significantly: - Tie the SOURCE of the upper FET and the DRAIN of the lower FET as close as possible; - Use the shortest low-impedance trace between the SOURCE of the lower FET and the power ground; - Tie the GND of the ISL6605 closely to the SOURCE of the lower FET. A resistor placement of RBOOT, as shown in Figure 5, in the earlier design is recommended; it helps eliminate the overcharge of the BOOT capacitor, in terms of voltage stress across the BOOT to PHASE. When needed, 1 to 2 Ohm RBOOT is sufficient and has little impact on the overall efficiency. However, a design with good layout and using MOSFETs with low parasitic lead inductances, such as multi-SOURCE leads devices (SO-8 and LFPAK), is generally not required such a resistor. When placing the QFN part on the board, no vias or trace should be running in between pin numbers 1 and 8 since a small piece of copper is underneath the corner for the orientation. In addition, connecting the thermal pad of the QFN part to the power ground with a via, or placing a low noise copper plane underneath the SOIC part is strongly recommended for high switching frequency, high current applications. This is for heat spreading and allows the part to achieve its full thermal potential. 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 FREQUENCY (KHZ) 0 100 200 300 400 500 600 700 800 900 1000 0 200 400 600 800 1000 1200 1400 1600 1800 2000 QU=50nC QL=50nC QU=50nC QL=100nC QU=100nC QL=200nC QU=20nC QL=50nC FIGURE 2. POWER DISSIPATION VS. FREQUENCY PWM ISL6605 499K GND FIGURE 3. 499k Ω RESISTOR PHASE Negative Spike FIGURE 4. TYPICAL PHASE NODE VOLTAGE WAVEFORM ISL6605 BOOT PHASE CBOOT RBOOT FIGURE 5. RESISTOR PLACEMENT FOR THE RBOOT |
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