5

FN9091.5

January 4, 2005

Functional Pin Description

Note: Pin numbers refer to the SOIC package. Check

PINOUT diagrams for QFN pin numbers.

UGATE (Pin 1)

Upper gate drive output. Connect to gate of high-side power

N-Channel MOSFET.

BOOT (Pin 2)

Floating bootstrap supply pin for the upper gate drive.

Connect the bootstrap capacitor between this pin and the

PHASE pin. The bootstrap capacitor provides the charge to

turn on the upper MOSFET. See the Bootstrap Diode and

Capacitor section under DESCRIPTION for guidance in

choosing the appropriate capacitor value.

PWM (Pin 3)

The PWM signal is the control input for the driver. The PWM

signal can enter three distinct states during operation (see the

three-state PWM Input section under DESCRIPTION for further

details). Connect this pin to the PWM output of the controller.

GND (Pin 4)

Ground pin. All signals are referenced to this node.

LGATE (Pin 5)

Lower gate drive output. Connect to gate of the low-side

power N-Channel MOSFET.

VCC (Pin 6)

Connect this pin to a +5V bias supply. Place a high quality

bypass capacitor from this pin to GND.

EN (Pin 7)

Enable input pin. Connect this pin to HIGH to enable and

LOW to disable the IC. When disabled, the IC draws less

than 1

µA bias current.

PHASE (Pin 8)

Connect this pin to the source of the upper MOSFET and the

drain of the lower MOSFET. This pin provides a return path

for the upper gate driver.

Thermal Pad (in QFN only)

In the QFN package, the pad underneath the center of the

IC is a thermal substrate. The PCB “thermal land” design

for this exposed die pad should include thermal vias that

drop down and connect to one or more buried copper

plane(s). This combination of vias for vertical heat escape

and buried planes for heat spreading allows the QFN to

achieve its full thermal potential. This pad should be either

grounded or floating, and it should not be connected to

other nodes. Refer to TB389 for design guidelines.

Description

Operation

Designed for speed, the ISL6605 MOSFET driver controls both

high-side and low-side N-Channel FETs from one externally

provided PWM signal.

A rising edge on PWM initiates the turn-off of the lower

MOSFET (see Timing Diagram). After a short propagation

section. Adaptive shoot-through circuitry monitors the

LGATE voltage and determines the upper gate delay time

below 1V. This prevents both the lower and upper MOSFETs

from conducting simultaneously or shoot-through. Once this

delay period is completed the upper gate drive begins to rise

A falling transition on PWM indicates the turn-off of the upper

MOSFET and the turn-on of the lower MOSFET. A short

through circuitry determines the lower gate delay time,

and the lower gate is allowed to rise after the upper MOSFET

gate-to-source voltage drops below 1V. The lower gate then

Timing Diagram

PWM

UGATE

LGATE

ISL6605