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ADSP-BF525ABCZ-5 Datasheet(PDF) 6 Page - Analog Devices |
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ADSP-BF525ABCZ-5 Datasheet(HTML) 6 Page - Analog Devices |
6 / 88 page Rev. D | Page 6 of 88 | July 2013 ADSP-BF522/ADSP-BF523/ADSP-BF524/ADSP-BF525/ADSP-BF526/ADSP-BF527 The SDRAM controller can be programmed to interface to up to 128M bytes of SDRAM. A separate row can be open for each SDRAM internal bank and the SDRAM controller supports up to 4 internal SDRAM banks, improving overall performance. The asynchronous memory controller can be programmed to control up to four banks of devices with very flexible timing requirements for a wide variety of devices. Each bank occupies a 1M byte segment regardless of the size of the devices used, so that these banks are only contiguous if each is fully populated with 1M byte of memory. NAND Flash Controller (NFC) The ADSP-BF52x processors provide a NAND flash controller (NFC). NAND flash devices provide high-density, low-cost memory. However, NAND flash devices also have long random access times, invalid blocks, and lower reliability over device lifetimes. Because of this, NAND flash is often used for read- only code storage. In this case, all DSP code can be stored in NAND flash and then transferred to a faster memory (such as SDRAM or SRAM) before execution. Another common use of NAND flash is for storage of multimedia files or other large data segments. In this case, a software file system may be used to manage reading and writing of the NAND flash device. The file system selects memory segments for storage with the goal of avoiding bad blocks and equally distributing memory accesses across all address locations. Hardware features of the NFC include: • Support for page program, page read, and block erase of NAND flash devices, with accesses aligned to page boundaries. • Error checking and correction (ECC) hardware that facili- tates error detection and correction. • A single 8-bit external bus interface for commands, addresses, and data. • Support for SLC (single level cell) NAND flash devices unlimited in size, with page sizes of 256 and 512 bytes. Larger page sizes can be supported in software. • Capability of releasing external bus interface pins during long accesses. • Support for internal bus requests of 16 bits. • DMA engine to transfer data between internal memory and NAND flash device. One-Time Programmable Memory The processor has 64K bits of one-time programmable non- volatile memory that can be programmed by the developer only one time. It includes the array and logic to support read access and programming. Additionally, its pages can be write protected. OTP enables developers to store both public and private data on-chip. In addition to storing public and private key data for applications requiring security, it also allows developers to store completely user-definable data such as customer ID, product ID, MAC address, etc. Hence, generic parts can be shipped, which are then programmed and protected by the developer within this non-volatile memory. I/O Memory Space The processor does not define a separate I/O space. All resources are mapped through the flat 32-bit address space. On-chip I/O devices have their control registers mapped into memory-mapped registers (MMRs) at addresses near the top of the 4G byte address space. These are separated into two smaller blocks, one which contains the control MMRs for all core func- tions, and the other which contains the registers needed for setup and control of the on-chip peripherals outside of the core. The MMRs are accessible only in supervisor mode and appear as reserved space to on-chip peripherals. Booting The processor contains a small on-chip boot kernel, which con- figures the appropriate peripheral for booting. If the processor is configured to boot from boot ROM memory space, the proces- sor starts executing from the on-chip boot ROM. For more information, see Booting Modes on Page 18. Event Handling The event controller on the processor handles all asynchronous and synchronous events to the processor. The processor pro- vides event handling that supports both nesting and prioritization. Nesting allows multiple event service routines to be active simultaneously. Prioritization ensures that servicing of a higher-priority event takes precedence over servicing of a lower-priority event. The controller provides support for five different types of events: • Emulation — An emulation event causes the processor to enter emulation mode, allowing command and control of the processor via the JTAG interface. • RESET — This event resets the processor. • Nonmaskable Interrupt (NMI) — The NMI event can be generated by the software watchdog timer or by the NMI input signal to the processor. The NMI event is frequently used as a power-down indicator to initiate an orderly shut- down of the system. • Exceptions — Events that occur synchronously to program flow (in other words, the exception is taken before the instruction is allowed to complete). Conditions such as data alignment violations and undefined instructions cause exceptions. • Interrupts — Events that occur asynchronously to program flow. They are caused by input signals, timers, and other peripherals, as well as by an explicit software instruction. Each event type has an associated register to hold the return address and an associated return-from-event instruction. When an event is triggered, the state of the processor is saved on the supervisor stack. The processor event controller consists of two stages, the core event controller (CEC) and the system interrupt controller (SIC). The core event controller works with the system interrupt |
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