R1EX24008ASAS0I/R1EX24008ATAS0I

R10DS0210EJ0100 Rev.1.00

Page 6 of 15

Nov 08, 2013

Pin Function

Serial Clock

(SCL)

The SCL pin is used to control serial input/output data timing. The SCL input is used to positive edge clock data into

EEPROM device and negative edge clock data out of each device. Maximum clock rate is 400 kHz.

Serial Input/Output Data

(SDA)

The SDA pin is bidirectional for serial data transfer. The SDA pin needs to be pulled up by resistor as that pin is open-

Except for a start condition and a stop condition which will be discussed later, the SDA transition needs to be completed

during the SCL low period.

Data Validity

(SDA data change timing waveform)

SCL

SDA

Data

change

Data

change

Note:

High-to-low and low-to-high change of SDA should be done during the SCL low period.

Device Address

(A0, A1, A2)

Two devices can be wired for one common data bus line as maximum. Device address pins are used to distinguish each

matches corresponding hard-wired device address pins A0 to A2, that one device can be activated.

Pin Connections for A0 to A2

Memory size

Max connect

number

Pin connection

Note

A2

A1

A0

8k bit

2

1

×*

2

×*

2

Use A0,A1 for memory address a8and a9

2. Floating state can be possible,

because it is not connected inside.

Write Protect

(WP)

When the Write Protect pin (WP) is high, the write protection feature is enabled and operates as shown in the following

table.

Also, acknowledgment "0" is outputted after inputting device address and memory address. After inputting write data,

acknowledgment "1""(NO ACK) is outputted.

When the WP is low, write operation for all memory arrays are allowed. The read operation is always activated

irrespective of the WP pin status.

Write Protect Area

WP pin status

Write protect area

8k bit

Full (8k bit)

Normal read/write operation