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RNA53A27F Datasheet(PDF) 3 Page - Renesas Technology Corp |
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RNA53A27F Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 7 page RNA53A27F Target Specification R03DS0022EJ0300 Rev.3.00 Page 3 of 6 Jun 26, 2013 Pin Arrangement 1 ROSC SLP MR 4 3 2 S0 VOUT VREFO VDD GND 8 7 (Top view) 6 5 Mark Indication (1) (2) (3) N 0 2 (1) Year code The last digit of year (2) Month code Starting in January "A", "B", "C", "D", "E", "F", "G", "H", "J", "K", "L", "M" (3) Week code View week of month, 1 week → "1" Pin Description Pin No. Terminal Marking Terminal Name I/O Function 1 ROSC Oscillation control resistance installation terminal — • 1.1 MΩ is installed between GND usually. • Delay adjustment range of resistance: 650(kΩ) to 1.35(MΩ) 2 SLP Sleep mode control I • L: Sleep mode (Power-supply current becomes several μA) • H: Usually mode • Terminal is open, Pull-down in GND 3 MR Manual reset input I • Low is input, 5pin(VOUT) output the low level Set the low pulse width by value is longer 3 μs • Terminal open, pull-up in VDD 4 GND GND — • Sorcing 0 V. 5 VOUT Reset output O • Power-supply voltage reaches the value below the detection voltage, low is output • Low level is input to MR terminal, low is output • Open drain output • Range pull-up resistance: 10(kΩ) to 100(kΩ) 6 VREFO Standard voltage output O • Standard voltage (3.05 V typ) for AD/DA is output • Outside puts capacity (0.1 μF) by pursuant for microcomputer 7 VDD Power-supply terminal — • Sorcing power-supply voltage. 8 S0 Delay time switch I • Delay time is switched. Low: 50 (ms), High: 100 (ms) • Terminal is open, pull-up in Vdd |
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