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R5F2154CGKFP Datasheet(PDF) 6 Page - Renesas Technology Corp |
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R5F2154CGKFP Datasheet(HTML) 6 Page - Renesas Technology Corp |
6 / 81 page R8C/54E Group, R8C/54F Group, R8C/54G Group, R8C/54H Group 1. Overview R01DS0043EJ0200 Rev.2.00 Page 6 of 78 Sep 05, 2012 Table 1.5 R8C/54G Group Specifications (1) Item Function Description CPU Central processing unit R8C CPU core • Number of fundamental instructions: 89 • Minimum instruction execution time: 31.25 ns (CPU clock = 32 MHz, VCC = 2.7 V to 5.5 V) • Multiplier: 16 bits × 16 bits 32 bits • Multiply-accumulate instruction: 16 bits × 16 bits + 32 bits 32 bits • Operating mode: Single-chip mode (address space: 1 Mbyte) Memory ROM, RAM, data flash Refer to Table 1.11 R8C/54G Group Product List. Voltage detection Voltage detection circuit • Power-on reset • Voltage detection with three check points (the detection levels for voltage detection 0 and voltage detection 1 can be selected.) I/O ports Programmable I/O ports • Input only: 1 • CMOS I/O: 43, selectable pull-up resistor • Peripheral mapping controller (PMC) allows communication function priority pin assignment selection. Clock Clock generation circuits • 4 circuits: XIN clock oscillation circuit, high-speed on-chip oscillator (with frequency adjustment function), low-speed on-chip oscillator, PLL frequency synthesizer (up to 32 MHz), multiplied by 2, 4, 6, or 8 • Oscillation stop detection: XIN clock oscillation stop detection function • Frequency divider circuit: Divided by 1, 2, 4, 8, or 16 can be selected • Low-power mode: Standard operating mode (high-speed clock, high-speed on-chip oscillator, low-speed on-chip oscillator, PLL operating), wait mode, stop mode Interrupts • Number of interrupt vectors: 69 • External interrupt inputs: 9 (INT × 5, key input × 4) • Priority levels: 7 Event link controller (ELC) • Events output from peripheral functions can be linked to events input to different peripheral functions. (22 sources × 7 types of event link operations) • Events can be handled independently from interrupt requests. Watchdog timer • 14 bits × 1 (with prescaler) • Selectable reset start function • Selectable low-speed on-chip oscillator for the watchdog timer DTC (data transfer controller) • 1 channel • Activation sources: 36 • Transfer modes: 2 (normal mode, repeat mode) |
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