THL3512_Rev.1.02_E

11

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THine Electronics, Inc.

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3-wire to 2-pair bridge function

When the MODE pin is set to high, the serial interface for writing to registers becomes 3-wire serial CMOS level input

(CSn, CK, SI), which is converted to 2-wire serial and transferred to the LVDS output pins.

- While the CSn is active low, the data input SI is latched and transferred to the LVDS output SDA_OUT on the rising

edges of the clock input SCK. There is about 10ns setup time between the clock output SCL_OUT and the data output

SDA_OUT.

- When the CSn falls, “Header Condition” is generated on 2-pair LVDS output.

- After the CSn rises, an active-low pulse "End Pulse” (the pulse width: 40ns typ) is added on the clock output

SCL_OUT.

- When the CSn rises, the data output SDA_OUT is forced high. In the result, the low to high transition of the clock out-

put SCL_OUT "End Pulse” occurs while the data output SDA_OUT is high

< 3-wire to 2-pair bridge >

2-pair to 2-pair repeater function

When the MODE pin is set to low, the serial interface for writing to registers becomes 2-pair serial LVDS input

(SCL_INp/SCL_INn, SDA_INp/SDA_INn). The timing between the clock and the data is compensated and then they are

transferred to the LVDS output pins.

- The data input SCL_IN is latched and transferred to the LVDS output SDA_OUT on the rising edges of the clock input

SCL_IN. There is about 10ns setup time between the clock output SCL_OUT and the data output SDA_OUT.

- The “Header Condition” is regenerated and transferred to the output.

< 2-pair to 2-pair repeater function >

SCL_INp (SCK)

SDA_INp (SI)

SCL_INn (CSn)

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6

76

5432

1

076

7

6543

2

1

0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6

76

5432

1

076

7

6543

2

1

0

“1st Byte“

“2nd Byte“

“Last Byte“

End Pulse

Header Condition

SCL_OUT

SDA_OUT

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6

7654

32

1

0

7

6

765

432

1

Header Condition

SCL_IN

SDA_IN

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6 bit5 bit4 bit3 bit2 bit1 bit0

bit7 bit6

76

5432

1

076

76543

2

1

0

“1st Byte“

“2nd Byte“

“Last Byte“

SCL_OUT

SDA_OUT