UPD16715A datasheet(11/16 Pages) NEC

Part #	UPD16715A

Description	384-OUTPUT TFT-LCD SOURCE DRIVER COMPATIBLE WITH 64-GRAY SCALES

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Manufacturer	NEC [NEC]

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Data Sheet S13944EJ2V0DS00

11

µµµµ PD16715A

Electrical Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V

±±±± 0.3 V, VDD2 = 11.0 V

V, VSS1 = VSS2 = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Input Leak Current

IIL

±1.0

µA

High-Level Output Voltage

VOH

STHR (STHL), IOH = 0 mA

VDD1

− 0.1

VDD1

V

Low-Level Output Voltage

VOL

STHR (STHL), IOL = 0 mA

0.1

V

V0 pin, V5 pin

0.31

0.8

mA

γ -Corrected Supply Current

Iγ

VDD2 = 13 V,

V0 to V4 = V5 to V9 = 6.0 V

V4 pin, V9 pin

–0.8

–0.31

mA

IVOH

VX = 8.0 V, VOUT = 6.0 V

–0.25

mA

Driver Output Current

IVOL

VX = 1.0 V, VOUT = 3.0 V

0.25

mA

Output Voltage Deviation

∆VO

Input data

±20

mV

Average Output Voltage

Variation

∆VAV

Input data

±10

mV

Output Voltage Range

VO

Input data

VDD2 +0.1

VDD2 – 0.1

V

Logic Part Dynamic Current

Consumption

IDD1

VDD1 = 3.6 V, TA = 25°C

1.5

8

mA

Driver Part Dynamic Current

Consumption

IDD2

VDD1 = 3.0 V, VDD2 = 13.5 V, No loads,

TA = 25°C

3.5

8

mA

Cautions 1. The output voltage deviation refers to the voltage difference between adjoining output pins when

the display data is the same (within the chip).

2.

The average output voltage variation refers to the average output voltage difference between

chips. The average output voltage refers to the average voltage between chips when the

display data is the same.

3.

The STB cycle is defined to be 20

µµµµs at fCLK = 33 MHz.

4.

The TYP. values refer to an all black or all white input pattern. The MAX. value refers to the

measured values in the dot checkerboard input pattern.

5.

Refers to the current consumption per driver when cascades are connected under the

assumption of XGA single-sided mounting (8 units).

Switching Characteristics (TA = –10 to +75 °C, VDD1 = 3.3 V

±±±± 0.3 V, VDD2 = 11.0 V

V, VSS1 = VSS2 = 0 V)

Parameter

Symbol

Condition

MIN.

TYP.

MAX.

Unit

Start Pulse Delay Time

tPLH1

CL = 25 pF

9.1

14

ns

tPLH2

5.2

11

µs

tPLH3

9.9

17

µs

tPHL2

5.3

11

µs

Driver Output Delay Time

tPHL3

CL = 50 pF, RL = 50 k

Ω

10.4

17

µs

CI1

STHR (STHL) excluded, TA = 25°C

5.8

15

pF

Input Capacitance

CI2

STHR (STHL),TA = 25°C

5.7

15

pF

+2.5

–2.0

•

+2.5

–2.0

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