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UPD16772 Datasheet(PDF) 4 Page - NEC |
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UPD16772 Datasheet(HTML) 4 Page - NEC |
4 / 5 page Data Sheet S14416EJ1V0DS00 4 µµµµPD16772 4. PIN FUNCTIONS Pin Symbol Pin Name Description S1 to S480 Driver output The D/A converted 64-gray-scale analog voltage is output. D00 to D05 D10 to D15 D20 to D25 D30 to D35 D40 to D45 D50 to D55 Display data input The display data is input with a width of 36 bits, viz., the gray scale data (6 bits) by 6 dots (2 pixels). DX0: LSB, DX5: MSB R,/L Shift direction control input These refer to the start pulse I/O pins when driver ICs are connected in cascade. The shift directions of the shift registers are as follows. R,/L = H: STHR input, S1 → S480, STHL output R,/L = L: STHL input, S480 → S1, STHR output STHR Right shift start pulse input/output STHL Left shift start pulse input/output These refer to the start pulse I/O pins when driver ICs are connected in cascade. Fetching of display data starts when H is read at the rising edge of CLK. R,/L = H (right shift): STHR input, STHL output R,/L = L (left shift): STHL input, STHR output The start pulse width (H level) for next-level drivers is 1CLK. CLK Shift clock input Refers to the shift register’s shift clock input. The display data is incorporated into the data register at the rising edge. At the rising edge of the 80th clock after the start pulse input, the start pulse output reaches the high level, thus becoming the start pulse of the next-level driver. If 82 clock pulses are input after input of the start pulse, input of display data is halted automatically. The contents of the shift register are cleared at the STB’s rising edge. STB Latch input The contents of the data register are transferred to the latch circuit at the rising edge. And, at the falling edge, the gray scale voltage is supplied to the driver. It is necessary to ensure input of one pulse per horizontal period. POL Polarity input POL = L: The S2n–1 output uses V0 to V4 as the reference supply. The S2n output uses V5 to V9 as the reference supply. POL = H: The S2n–1 output uses V5 to V9 as the reference supply. The S2n output uses V0 to V4 as the reference supply. S2n-1 indicates the odd output: and S2n indicates the even output. Input of the POL signal is allowed the setup time(tPOL-STB) with respect to STB’s rising edge. POL21, POL22 Data inversion input Data inversion can invert when display data is loaded. POL21/22 = H : Data inversion loads display data after inverting it. POL21/22 = L : Data inversion does not invert input data. POL21: D00 to D05, D10 to D15, D20 to D25 POL22: D30 to D35, D40 to D45, D50 to D55 LPC Low power control input The current consumption of VDD2 is lowered by controlling the constant current source of the output amplifier. This pin is pulled up to the VDD1 power supply inside the IC. For details, see 9. CURRENT CONSUMPTION REDUCTION FUNCTION. Bcont Bias control This pin can be used to finely control the bias current inside the output amplifier. When this fine-control function is not required, leave this pin open. For details, see 9. CURRENT CONSUMPTION REDUCTION FUNCTION. V0 to V9 γ -corrected power supplies Input the γ -corrected power supplies from outside by using operational amplifier. Make sure to maintain the following relationships. During the gray scale voltage output, be sure to keep the gray scale level power supply at a constant level. VDD2 − 0.1 V > V0 > V1 > V2 > V3 > V4 > 0.5 VDD2 > V5 > V6 > V7 > V8 > V9 > VSS2 + 0.1 V VDD1 Logic power supply 2.3 to 3.6 V VDD2 Driver power supply 8.5 V ± 0.5 V VSS1 Logic ground Grounding VSS2 Driver ground Grounding |
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