Data Sheet S13020EJ1V0DS00

2

BLOCK DIAGRAM

Note The internal resister doesn’t connect to input terminal of CTL1 (1 pin) and CTL2 (4 pin).

Therefore the input level must be “H” or “L” even if these pins aren’t used.

Gate

Control

Ref.

Voltage

Over Current

Detect

Over Current

Detect

OUT2

(Output2)

FLG2

(Flag Out2)

OUT1

(Output1)

FLG1

(Flag Out1)

UVLO

IN (Input)

CTL1

(Control Input1)

Thermal

Shutdown

2

1

CTL2

(Control Input2)

4

GND

6

8

5

7

3

Ref.

Voltage

Gate

Control