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AN1049 Datasheet(PDF) 11 Page - STMicroelectronics |
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AN1049 Datasheet(HTML) 11 Page - STMicroelectronics |
11 / 24 page where VF is the forward drop on the rectifier, Iq is the quiescent current of the IC, IGD the average current delivered to the gate of the MOSFET by the driver output (see "Power MOSFET") and Iext the current consumption of some other circuitry powered by the self-supply circuit. Table 3. Consumption of the self-supply circuit for different IC’s. Device Iqmax PSSmax L5991 10mA (15 + 0.6)V • (10 + 2)mA = 187 mW L5991A 10mA (9 + 0.6)V • (10 + 2)mA = 115 mW UC3842A/B 17mA (15 + 0.6)V • (17 + 5)mA = 343 mW Table 3 summarizes a comparison concerning the power demanded to the self-supply circuit under light load conditions by different IC’s. In addition to those considered in table 1 and 2, table 3 includes also the L5991A, the version of L5991 with VTH = 9V (max.) and a minimum operating voltage of 8.2V (max.). The table assumes IGD =2mA for L5991, L5991A (due to their standby function) and IGD =5mA for the UC384XA/B, Iext = 0, VCC =15V (9V for L5991A), VF = 0.6V and maximum Iq. If the start-up circuit is (a) or (b), a low VCC will cause higher power to be dissipated in RSTART, but will also lead to a lower PSS. In practical cases, the contribution of VCC to PSS is prevailing thus the total power consumption PSTART + PSS will be lower at low VCC. If the start-up circuit is (c) a low VCC requires the use of the NPN transistor and the 47 k Ω resistor to turn off the start-up MOS, but is definitely advantageous in terms of consumption. As a result, it is advisable to keep VCC as low as possible whatever start-up circuit is used. As to this concept, the L5991A is particularly advantageous. The undervoltage lockout hysteresis, how- ever, is small (9 - 8.2 = 0.8 V) and this calls for a bigger CSUPPLY which, in turn, requires a lower RSTART for the same wake-up time. As a result, PSTART will be considerably higher. Power MOSFET The incidence of the MOSFET on power losses at light load depends basically on the switching fre- quency. Leaving out conduction losses, which can be neglected in this context, the power dissipation due to the MOSFET under light load conditions consists of three contributions: 1 -Turn-on losses, due to the discharge of the total capacitance of the drain node inside the MOSFET. It is possible to separate two different contributions to the total drain capacitance (CDrain): Coss, the in- ternal capacitance of the MOSFET, modulated by the drain voltage (manufacturers specify the value @ VDS = 25V), and CDext, the external parasitic capacitance due to the transformer and to the layout of the circuit. In practice, it is possible to estimate CDrain from the drain voltage oscillation occuring af- ter the secondary current has run dry in DCM operation (see fig. 9). In fact, when the transformer is discharged, the primary inductance starts resonating with CDrain and the oscillation period is: TRES ≈ 2π ⋅ √ Lp ⋅ CDrain (26). Turn-on losses depend on the input voltage in a non-monotonic way. As shown in fig. 9, the value of the drain voltage at turn-on (VDon) in DCM operation is affected by the above mentioned oscillation. An input voltage increase, despite raising the settling value of the oscillation, may lead to a lower value at turn-on because of a particular combination of TON, TFW, TDEAD and TRES. 2 -Turn-off losses, due to the crossing of the active region that causes a voltage-current overlapping, as shown schematically in figure 10. The fall time (Tf) of a given MOSFET depends on the driver capa- bility (1.6A peak) and can be controlled with a series resistor placed between pin 10 and the gate of the MOSFET. The parasitic inductances (basically, the one located between source and ground) limit the maximum di/dt rate achievable. The rate of rise of VDS depends mainly on CDrain. 3 - Gate drive losses, related to the charge to be delivered to the gate each time the MOSFET is turned on. This charge, supplied at fSB rate, results in an equivalent DC current IGD. The parameter to be consid- ered is the total gate charge (Qg) of the device, evaluated at the gate voltage delivered by the L5991. AN1049 APPLICATION NOTE 11/24 |
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