MX66L1G45G datasheet(9/124 Pages) MCNIX

Part #	MX66L1G45G

Description	3V 1G-BIT [x 1/x 2/x 4] CMOS MXSMIO

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Manufacturer	MCNIX [Macronix International]

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MX66L1G45G

REV. 1.0, OCT. 01, 2014

P/N: PM2018

6. DATA PROTECTION

During power transition, there may be some false system level signals which result in inadvertent erasure or

programming. The device is designed to protect itself from these accidental write cycles.

The state machine will be reset as standby mode automatically during power up. In addition, the control register

architecture of the device constrains that the memory contents can only be changed after specific command

sequences have completed successfully.

In the following, there are several features to protect the system from the accidental write cycles during VCC power-

up and power-down or from system noise.

• Valid command length checking: The command length will be checked whether it is at byte base and completed

on byte boundary.

• Write Enable (WREN) command: WREN command is required to set the Write Enable Latch bit (WEL) before

other command to change data.

• Deep Power Down Mode: By entering deep power down mode, the flash device also is under protected from

writing all commands except Release from deep power down mode command (RDP) and Read Electronic

Signature command (RES), Erase/Program suspend command, Erase/Program resume command and softreset

command.

• Advanced Security Features: there are some protection and security features which protect content from

inadvertent write and hostile access.

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Generalplus Technology ...	GPR25L6403F	1Mb / 47P	3V, 64M-BIT [x 1/x 2/x 4] CMOS MXSMIO (SERIAL MULTI I/O) FLASH MEMORY
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