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AN1696 Datasheet(PDF) 9 Page - STMicroelectronics |
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AN1696 Datasheet(HTML) 9 Page - STMicroelectronics |
9 / 11 page 9/11 AN1696 APPLICATION NOTE For a short time (before overcurrent/undervoltage protections are triggered), the unbroken sections are able to deliver such high current maintaining the load voltage in the right range. This in turn causes VC(OUT) to be lower than VLOAD and the OR-ing FET will be turned off whenever VC(OUT) = VC(OUT)-OFF. It is possible to obtain the value of the current necessary to push VC(OUT) at VC(OUT)-OFF: 3.0 DEMO-BOARD BEHAVIOUR The aim of this demo-board is mainly to show the operation of current sharing section, drawing the attention also to the management of the OR-ing FET. For this reason no protection have been introduced to prevent in- rush current: it is not possible to actually insert or remove a daughter board during normal operating, neverthe- less it is recommended to simulate a fault by enabling/disabling one section through the switch SW1 (it shorts to GND the soft-start pin). Once all the daughter board are inserted (with the switches on the "ON" position), the system is ready to be powered-up. Measuring the three output currents and varying the load continuously, it is possible to see the load share ac- curacy (fig. 7); obviously, at light load, the accuracy is not so high because is higher the weight of both the mis- matches between relevant components and the noise is higher. At full load (10A) the maximum error is lower than 2.5%. Fig. 8 shows the behaviour of the system whenever a fault condition appears on section 1 when the three sec- tions are operating supplying a total load of 10A (each of them carries about 3.3A); in particular it is simulated a short of the low side FET of the synchronous rectifier section 1. If no OR-ing element were implemented, this could cause a short circuit condition on the other two sections (UV and/or overcurrent protection could be activated): here the gate driver circuit opens the OR-ing FET preventing current flow from the load to the output of section 1 and the output voltage experiences only a very small drop. The currents of section 2 and 3 grow up to 5A. I RE V 1 R DS ON () ----------------------- V LOA D 1 R9 R8 R9 + ---------------------- 1 R5 R7 -------- + ⋅ – V PU M P R5 R7 -------- ⋅ + ⋅ ⋅ = Figure 7. Load share accuracy Figure 8. Fault on one section -30 -25 -20 -15 -10 -5 0 5 10 15 20 25 30 10 20 30 40 50 60 70 80 90 100 Output current [%] IOUT1 IOUT2 IOUT3 |
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