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L6207 Datasheet(PDF) 7 Page - STMicroelectronics |
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L6207 Datasheet(HTML) 7 Page - STMicroelectronics |
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7 / 53 page  7/53 AN1762 APPLICATION NOTE where IOUT is the output current. With fast decay, instead, recirculating current recharges the capacitor, causing the supply voltage to exceed the nominal voltage. This can be very dangerous if the nominal supply voltage is close to the maximum recommended supply voltage (52V). In fast decay the supply voltage ripple is about: , always assuming that the power supply does not recharge the capacitor, and neglecting the output current ripple and the dead-time. Usually (if C > 100 µF) the capacitance role is much less than the ESR, then supply voltage ripple can be estimated as: IOUT · ESR in slow decay 2 · IOUT · ESR in fast decay For Example, if a maximum ripple of 500mV is allowed and IOUT = 2A, the capacitor ESR should be lower than: in slow decay, and in fast decay. Actually, current sunk by VSA and VSB pins of the device is subject to higher peaks due to reverse recovery charge of internal freewheeling diodes. Duration of these peaks is, tough, very short, and can be filtered using a small value (100÷200 nF), good quality ceramic capacitor, connected as close as possible to the VSA, VSB and GND pins of the IC. Bulk capacitor will be chosen with maximum operating voltage 25% greater than the maximum supply voltage, considering also power supply tolerances. For example, with a 48V nominal power supply, with 5% tolerance, maximum voltage is 50.4V, then operating voltage for the capacitor should be at least 63V. 3.4 Layout Considerations Working with devices that combine high power switches and control logic in the same IC, careful attention has to be paid to the PCB layout. In extreme cases, Power DMOS commutation can induce noises that could cause improper operation in the logic section of the device. Noise can be radiated by high dv/dt nodes or high di/dt paths, or conducted through GND or Supply connections. Logic connections, especially high-impedance nodes (actually all logic inputs, see further), must be kept far from switching nodes and paths. With the L6205, L6206, L6207, in particular, external components for the charge pump circuitry should be connected together through short paths, since these components are subject to voltage and current switching at relatively high frequency (600kHz). Primary mean in minimizing conducted noise is working on a good GND layout (see Figure 7). I OUT 2 ESR ⋅ t ON t OFF + C ---------------------------- + ⋅ ESR 0.5 V 2A ------------ < 250m Ω = ESR 1 2 --- 0.5 V 2A ------------ ⋅ < 125m Ω = |
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Similar Description - L6207 |
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