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TQM879008 Datasheet(PDF) 6 Page - TriQuint Semiconductor |
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TQM879008 Datasheet(HTML) 6 Page - TriQuint Semiconductor |
6 / 10 page TQM879008 1.5-2.7 GHz ½ W Digital Variable Gain Amplifier Datasheet: Rev I 01-06-14 - 6 of 10 - Disclaimer: Subject to change without notice © 2013 TriQuint www.triquint.com Serial Control Interface The TQM879008 has a CMOS SPITM input compatible serial interface. This serial control interface converts the serial data input stream to parallel output word. The input is 3-wire (CLK, LE and SID) SPITM input compatible. At power up, the serial control interface resets the DSA to the minimum gain state. The 6-bit SID (Serial Input Data) word is loaded into the register on rising edge of the CLK, MSB first. When LE is high, CLK is internally disabled. Serial Control Timing Characteristics (Test conditions: V CC = +5 V, Temp.=25°C) Parameter Condition Min Max Units Clock Frequency 50% Duty Cycle 10 MHz LE Setup Time, tLESUP after last CLK rising edge 10 ns LE Pulse Width, tLEPW 30 ns SERIN set-up time, tSDSUP before CLK rising edge 10 ns SERIN hold-time, tSDHLD after CLK rising edge 10 ns LE Pulse Spacing tLE LE to LE pulse spacing 630 ns Propagation Delay tPLO LE to Parallel output valid 30 ns Serial Control DC Logic Characteristics (Test conditions: V CC = +5 V, Temp.=25°C) Parameter Condition Min Max Units Input Low State Voltage, VIL 0 0.8 V Input High State Voltage, VIH 2.4 VCC V Input Current, IIH / IIL On SID, LE and CLK pins −10 +10 µA SERIN Control Logic Truth Table Timing Diagram 6-Bit Control Word Attenuation State CLK is internally disabled when LE is high MSB LSB SID CLK LE D5-D0 MSB-LSB D5-D0 MSB-LSB t SDSUP t SDHLD t LESUP t LEPW t PLO D5 D4 D3 D2 D1 D0 1 1 1 1 1 1 Reference : IL 1 1 1 1 1 0 0.5 dB 1 1 1 1 0 1 1 dB 1 1 1 0 1 1 2 dB 1 1 0 1 1 1 4 dB 1 0 1 1 1 1 8 dB 0 1 1 1 1 1 16 dB 0 0 0 0 0 0 31.5 dB Any combination of the possible 64 states will provide an attenuation of the sum of bits selected. |
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