TQP4M9072

High Linearity 6-Bit, 31.5 dB Digital Step Attenuator

Datasheet: Rev O 11-20-14

- 3 of 12 -

Disclaimer: Subject to change without notice

© 2014 TriQuint

www.triquint.com

Serial Control Interface

the serial control interface resets the DSA to the minimum gain state. The 6-bit SID (Serial Input Data) word is loaded

into the register on rising edge of the CLK, MSB first. When LE is high, CLK is internally disabled.

Parameter

Condition

Min

Max

Units

Clock Frequency

50% Duty Cycle

10

MHz

after last CLK rising edge

10

ns

30

ns

before CLK rising edge

10

ns

after CLK rising edge

10

ns

LE to LE pulse spacing

630

ns

Parameter

Condition

Min

Max

Units

0

0.8

V

2.4

V

On SOD pin

2.0

V

On SOD pin

0

0.8

V

On SID, LE and CLK pins

−10

+10

µA

0

0.8

V

2.8

V

On SID, LE and CLK pins

−10

+10

µA

SERIN Control Logic Truth Table

Timing Diagram

6-Bit Control Word

Attenuation

State

CLK is internally disabled when LE is high

MSB

LSB

D5

D4

D3

D2

D1

D0

1

1

1

1

1

1

Reference : IL

1

1

1

1

1

0

0.5 dB

1

1

1

1

0

1

1 dB

1

1

1

0

1

1

2 dB

1

1

0

1

1

1

4 dB

1

0

1

1

1

1

8 dB

0

1

1

1

1

1

16 dB

0

0

0

0

0

0

31.5 dB

Any combination of the possible 64 states will provide an

attenuation of approximately the sum of bits selected