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DCR1110F52 Datasheet(PDF) 7 Page - Dynex Semiconductor |
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DCR1110F52 Datasheet(HTML) 7 Page - Dynex Semiconductor |
7 / 10 page SEMICONDUCTOR DCR1110F52 7/10 www.dynexsemi.com Fig.10 Multi-cycle surge current Fig.11 Single-cycle surge current Fig.12 Stored charge vs di/dt Fig.13 Reverse recovery current vs di/dt 1 10 100 1 10 100 Number of cycles Conditions: Tcase = 125 C VR =0 Pulse width = 10ms 0 1 2 3 0 5 10 15 20 25 30 35 40 1 10 100 Pulse width, tP - (ms) I2t ITSM Conditions: Tcase= 125 C VR = 0 half-sine wave 0 1000 2000 3000 4000 5000 6000 7000 0 5 10 15 20 Rate of decay of on-state current, di/dt - (A/us) Q s typical = 1682.8*(di/dt) 0.4945 Conditions: Tj = 125°C, V peak ~ 3000V Vrm ~ 2200V snubber as appropriate to control reverse voltage 0 50 100 150 200 250 300 0 5 10 15 20 Rate of decay of on-state current, di/dt - (A/us) IRRtypical = 32.97*(di/dt) 0.7324 Conditions: Tj = 125°C, V peak ~ 3000V Vrm ~ 2200V snubber as appropriate to control reverse voltage |
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