4

LTC1329-10/

LTC1329-50/LTC1329A-50

TEMPERATURE (

°C)

0

3

2

1

0

–1

–2

–3

30

50

1329 G05

10

20

40

60

70

LTC1329-50

LTC1329-10

CODE

0

1.0

0.8

0.6

0.4

0.2

0

–0.2

–0.4

–0.6

–0.8

–1.0

64

128

160

1329 • TPC04

32

96

192 224

256

LTC1329-10/LTC1329-50 Full-

Scale Current vs Temperature

SUPPLY VOLTAGE (V)

0

2

1

0

–1

–2

35

1329 G06

12

46

7

LTC1329-50

LTC1329-10

LTC1329-10/LTC1329-50

Supply Voltage Rejection

LTC1329-50 INL vs Code

the DAC current output can be biased from – 15V to 2V or

– 15V to 2.5V respectively.

supply must be kept free from noise and ripple by bypass-

ing directly to the ground plane.

SHDN (Pin 3): Shutdown. A logic low puts the chip

into Shutdown mode. The digital setting for the DAC is

retained.

CLK (Pin 4): Shift Clock. This clock synchronizes the serial

data in 3-wire mode. This pin has a Schmitt trigger input.

CS (Pin 5): Chip Select Input. In 3-wire mode, a logic low

on this CS pin enables the LTC1329. Upon power-up, a

logic high at CS puts the chip into pulse mode. If CS ever

goes low, the chip is configured in 3-wire mode until the

next power is cycled.

GND (Pin 6): Ground. Ground should be tied directly to a

ground plane.

–15

0.5

0.4

0.3

0.2

0.1

0

–0.1

–0.2

–0.3

–0.4

–0.5

–6

0

1329 G07

–12

–9

–3

3

6

LTC1329-50

LTC1329-10

LTC1329-10/LTC1329-50

Bias Voltage Rejection

(Full-Scale Current)

–15

50

40

30

20

10

0

–10

–20

–30

–40

–50

–6

0

1329 G08

–12

–9

–3

3

6

LTC1329-10

LTC1329-50

LTC1329-10/LTC1329-50

Bias Voltage Rejection

(Zero-Scale Current)

SUPPLY VOLTAGE (V)

2.7

6.5

6.0

5.5

5.0

4.5

4.0

3.5

3.0

2.5

2.0

1.5

3.7

4.7

5.2

1329 • TPC09

3.2

4.2

5.7

6.2

6.7

vs Supply Voltage