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LTC1428-50 Datasheet(PDF) 3 Page - Linear Technology |
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LTC1428-50 Datasheet(HTML) 3 Page - Linear Technology |
3 / 8 page 3 LTC1428-50 VCC = 5V, unless otherwise specified. (Notes 2, 3) RECO E DED OPERATI G CO DITIO S TYPICAL PERFORMANCE CHARACTERISTICS The q denotes specifications which apply over the full operating temperature range. Note 1: Absolute Maximum Ratings are those values beyond which the life of the device may be impaired. Note 2: Timing for all input signals is measured at 0.8V for a High-to-Low transition and at 2V for a Low-to-High transition. Note 3: Timing specifications are guaranteed by design but not tested. Note 4: This is the minimum time required for valid data transfer. CODE 0 – 1.0 – 0.8 – 0.4 – 0.2 0 1.0 0.4 64 128 160 1428-50 G01 – 0.6 0.6 0.8 0.2 32 96 192 224 256 VCC = 3.3V V(IOUT) = 2.5V TA = 25°C DNL vs Code Supply Voltage Rejection INL vs Code CODE 0 1.0 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 –1.0 64 128 160 1428-50 G02 32 96 192 224 256 VCC = 3.3V V(IOUT) = 2.5V TA = 25°C SYMBOL PARAMETER CONDITIONS MIN TYP MAX UNITS Serial Interface fCLK Clock Frequency q 2 MHz tCKS Setup Time, CLK ↓ Before CS↓ q 150 ns tCSS Setup Time, CS ↓ Before CLK↑ q 400 ns tDV CS ↓ to DOUT Valid See Test Circuits q 150 ns tDS DIN Setup Time Before CLK↑ q 150 ns tDH DIN Hold Time After CLK↑ q 150 ns tDO CLK ↓ to DOUT Valid See Test Circuits q 150 ns tCKHI CLK High Time q 200 ns tCKLO CLK Low Time q 250 ns tCSH CLK ↓ Before CS↑ q 150 ns tDZ CS ↑ to DOUT in Hi-Z See Test Circuits q 400 ns tCKH CS ↑ Before CLK↑ q 400 ns tCSLO CS Low Time fCLK = 2MHz (Note 4) q 4550 ns VCLK = 0V 400 ns tCSHI CS High Time q 400 ns SUPPLY VOLTAGE (V) 1 – 0.5 0 0.5 4 6 1428-50 G03 – 1.0 – 1.5 – 2.0 23 5 1.0 1.5 2.0 7 V(IOUT) = 2.5V TA = 25°C |
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