LTC1555L-1.8

5

and 6V. There is no power-up sequencing requirement for

to GND during shutdown (M0, M1 = 0V). A 2.2

µF low ESR

I/O (Pin 14): SIM Side I/O Pin. The pin is an open drain

output with a nominal pull-up resistance of 10k

Ω and

should be connected to the SIM I/O contact. The SIM card

must sink up to 1mA max when driving the I/O pin low due

to the internal pull-up resistors on the I/O and DATA pins.

The I/O pin is held active low during shutdown.

RST (Pin 15): Level Shifted Reset Output Pin. Should be

connected to the SIM RST contact.

CLK (Pin 16): Level Shifted Clock Output Pin. Should be

connected to the SIM CLK contact. Careful trace routing is

recommended due to fast rise and fall edge speeds.

M0

M1

M2

OPERATING MODE

0V

0V

0V

0V

0V

0V

Table 1. Truth Table

M2 (Pin 6): Mode Control Bit 2 (see Table 1). (Pin 6 was

previously used for soft-start control on the LTC1555.)

M1 (Pin 7): Mode Control Bit 1 (see Table 1).

M0 (Pin 8): Mode Control Bit 0 (see Table 1).

GND (Pin 9): Ground for Both the SIM and the Controller.

Should be connected to the SIM GND contact as well as to

bypassing is required to meet 10kV ESD specifications.

BLOCK DIAGRA

DDRV

OPTIONAL

1

µA

I/O

DATA

20k

10k

CLK

CIN

RST

M2

1.8V

RIN

GND

M1

M0

1

µF

I/O

CLK

RST

GND

0.1

µF

STEP-UP/

STEP-DOWN

CHARGE PUMP

DC/DC

CONVERTER

SIM

CONTROLLER

2.2

µF

UVLO

LTC1555L-1.8

1555L BD