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AN3318 Datasheet(PDF) 2 Page - STMicroelectronics

Part # AN3318
Description  This Application note presents the HSP061-4NY8 and its capability
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN3318 Datasheet(HTML) 2 Page - STMicroelectronics

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Location for HSP061-4NY8
AN3318
2/10
Doc ID 18263 Rev 1
1
Location for HSP061-4NY8
Many PCB parasitic elements may degrade the overall ESD performance of a system. The
recommendations below are aimed at optimizing ESD protection device placement and the
PCB layout to reach the best ESD performance possible.
The layout shown in Figure 1 may induce parasitic inductances responsible for artificial
overvoltages directly applied on the IC to be protected.
A very simple calculation shows that for a 8 kV ESD surge according to IEC61000-4-2, the
overvoltage due to parasitic inductances may be really significant, as shown in Figure 2.
Assuming that each inductance value is 5 nH (corresponds to metal track 5 mm long):
then the overvoltage seen by the IC is:
This parasitic inductance must be reduced as much as possible by shortening the ground
path return to the GND via.
To avoid ESD propagation on the PCB, the ESD protection must be placed as close as
possible to the ESD source with the layout given in the datasheet.
The layout given in the datasheet reduces parasitic inductance. It is important to connect the
connector on one side of the HSP and the transceiver on the other side. The GND via on
both sides must be used.
As ESD stress can be propagated on both sides of the cable, a protection device on each
end of the cable is required.
Figure 1.
Non-optimized location for
HSP061-4NY8
Figure 2.
Significant overvoltages due
to non-optimal location of
HSP061-4NY8
IC to
protect
Via to
GND
1
2
4
5
6
8
37
Via to
Via to
GND
GND
Via to
IC to
protect
Via to
GND
V
dt
di
L
VIC
ESD surge is 8 kV with 1 ns
rise time, this leads to 38 A/ns
GND layer
GND
di
dt
= 38 A/ns
di
dt
V
= V +
IC
V
= V + 190 V
IC


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