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AN432 Datasheet(PDF) 7 Page - STMicroelectronics

Part # AN432
Description  All members of the ST62 Series of Microcontrollers
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Manufacturer  STMICROELECTRONICS [STMicroelectronics]
Direct Link  http://www.st.com
Logo STMICROELECTRONICS - STMicroelectronics

AN432 Datasheet(HTML) 7 Page - STMicroelectronics

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USING ST62xx I/O PORTS SAFELY
3 OPERATION OF SINGLE BIT INSTRUCTIONS
The ST62XX instruction set includes four different instructions operating on single bits.
The first two instructions use a read-modify-write cycle.
– SET Set Bit in Register
– RES Reset Bit in Register
– JRS Jump Relative IF Bit in Register is set
– JRR Jump Relative IF Bit in Register is reset
The single bit instructions read a whole byte (8 bits), perform an “AND” (RES, JRR) or “OR”
(SET, JRS) operation with a single bit mask operand (e.g 01h for bit 0, 04h for bit 2), and, in
the case of SET and RES, write the result back to the source.
Thus the whole byte is processed, even if only one bit is modified or tested. This causes some
constraints in using these instructions with the Data Register.
Table 2. Example for the operation of a single bit instruction
Restrictions in using SET and RES instructions
As an example, let us assume that one or more of the pins of the port are set to input mode.
A SET/RES operation on a bit of DR will read the state of the corresponding input pin instead
of the content of DR. After modifying the specified bit, the result will be written (as a byte) back
into DR.
Depending on the state of the specified inputs, the contents of DR may be changed. This can
cause a change of the input mode by accident, that is, depending on the state of the corre-
sponding bit in OR, the pin operation mode can be switched from input mode with pull-up to
input mode without pull-up (or vice-versa) or from interrupt mode to analog input (or vice-
versa). These side effects on the I/O port may be avoided if a copy of the DR content is kept
in a RAM location. Now SET/RES instructions can be executed on the RAM location, and the
result then written to DR as shown in Table 3.
RAM (Before)
RAM (After)
Address
Data
Address
Data
SET 3,085h
085h
055h
055h 01010101 B
085h
05Ch
OR 008h 00001000 B
05Ch 01011101 B


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