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UPD61P24GS Datasheet(PDF) 4 Page - NEC |
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UPD61P24GS Datasheet(HTML) 4 Page - NEC |
4 / 36 page µPD61P24 4 1. PROGRAM COUNTER (PC) ……… 10 BITS The program counter (PC) is a binary counter, which holds the address information for the program memory. Figure 1-1. Program Counter Organization PC 7 PC 6 PC 5 PC 4 PC 3 PC 2 PC 1 PC 0 PC 8 PC 9 PC Normally, the program counter contents are automatically incremented each time an instruction is executed, according to the number of instruction bytes. When executing a jump instruction (JMP0, JC, JF), the program counter indicates the jump destination. Immediate data or the data memory contents are loaded to all or some bits of the PC. When executing the call instruction (CALL0), the PC contents are incremented (+1) and saved into the stack memory. Then, a value needed for each jump instruction will be loaded. When executing the return instruction (RET), the stack memory contents are double incremented (+2) and loaded into the PC. When “all clear” is input or on reset, the PC contents are cleared to “000H”. 2. STACK POINTER (SP) ……… 2 BITS This 2-bit register holds the start address information for the stack area. The stack area is shared with the data memory. The SP contents are incremented, when the call instruction (CALL0) is executed. They are decremented, when the return instruction (RET) is executed. The stack pointer is cleared to “00B” after reset or “all clear” is input, and indicates the highest address FH for the data memory as the stack area. The figure below shows the relationship for the stack pointer and the data memory area. RC Data memory RD RE RF (SP) 11B 10B 01B 00B If the stack pointer overflows or underflows, it is determined that the CPU overflows, and the PC internal reset signal will be generated. |
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