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AN2077 Datasheet(PDF) 6 Page - STMicroelectronics |
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AN2077 Datasheet(HTML) 6 Page - STMicroelectronics |
6 / 19 page 6/19 EEPROM Emulation with STR71x 2.2 PROGRAM/ERASE CYCLE The requirement number of program/erase cycles is computed by dividing the needed number of erase cycles by the total number of Data-sets in the Flash banks (for example in Figure 1: n+m). When this number is still higher than the Flash write/erase endurance characteristics, a closer analysis is needed to understand when the Data-sets are updated: – When Data-sets need to be updated during operation, it is proposed to use a buffer in RAM and to save the data before shutting-down the microcontroller. – When Data-sets are updated only before a power-down sequence, it is proposed to increase the size of the Flash bank or to use a 3rd bank (see additional information in Section 3). 2.3 READ-WHILE-WRITE Most currently available Flash technologies must complete a program or erase operation be- fore code or data can be read from another memory block. There is a common misconception that EEPROM emulation can only be done when Read-While-Write functionality is imple- mented. Read-While-Write, when present, allows other memory blocks to be accessed during erasing and programming; this means that the CPU program does not need to be copied into RAM during programming/erasing. Read-While-Write does not prevent having a RAM buffer if access into the emulated-EEPROM is needed during programming. When Read-While-Write is not supported, program or erase suspend command can be used to temporarily read code. All STR71xF variants support program and erase suspend com- mands. 2.4 FLASH ORGANIZATION The concept described above shows the Flash bank split into 2 parts: – Data-set storage: which keeps all variable information, – Status bit storage: which keeps status of the Flash bank and of the Data-sets. Other organizations are possible (ex: to include the Data-set status bits inside each Data-set) for which users may see advantages for their application. 2.5 DATA-SET STATUS BITS Two status bits are proposed for each Data-set with the combinations shown in the following table. |
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