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LTC4300A-1 Datasheet(PDF) 8 Page - Linear Technology |
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LTC4300A-1 Datasheet(HTML) 8 Page - Linear Technology |
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8 / 16 page  LTC4300A-1/LTC4300A-2 8 4300a12fa OPERATION Another key feature of the connection circuitry is that it provides bidirectional buffering, keeping the backplane and card capacitances isolated. Because of this isolation, the waveforms on the backplane busses look slightly different than the corresponding card bus waveforms, as described here. Input to Output Offset Voltage When a logic low voltage, VLOW1, is driven on any of the LTC4300A’s data or clock pins, the LTC4300A regulates the voltage on the other side of the chip (call it VLOW2) to a slightly higher voltage, as directed by the following equation: VLOW2 = VLOW1 + 75mV + (VCC/R) • 100 where R is the bus pull-up resistance in ohms. For ex- ample, if a device is forcing SDAOUT to 10mV where VCC = 3.3V and the pull-up resistor R on SDAIN is 10k, then the voltage on SDAIN = 10mV + 75mV + (3.3/10000) • 100 = 118mV. See the Typical Performance Character- istics section for curves showing the offset voltage as a function of VCC and R. Propagation Delays During a rising edge, the rise-time on each side is deter- mined by the combined pull-up current of the LTC4300A boost current and the bus resistor and the equivalent capacitance on the line. If the pull-up currents are the same, a difference in rise-time occurs which is directly proportional to the difference in capacitance between the two sides. This effect is displayed in Figure 1 for VCC = 3.3V and a 10k pull-up resistor on each side (50pF on one side and 150pF on the other). Since the output side has less capacitance than the input, it rises faster and the effective tPLH is negative. There is a finite propagation delay, tPHL, through the con- nection circuitry for falling waveforms. Figure 2 shows the falling edge waveforms for the same VCC, pull-up resistors and equivalent capacitance conditions as used in Figure 1. An external NMOS device pulls down the volt- age on the side with 150pF capacitance; the LTC4300A pulls down the voltage on the opposite side, with a delay of 55ns. This delay is always positive and is a function of Start-Up When the LTC4300A first receives power on its VCC pin, either during power-up or during live insertion, it starts in an undervoltage lockout (UVLO) state, ignoring any activity on the SDA and SCL pins until VCC rises above 2.5V. For the LTC4300A-2, the part also waits for VCC2 to rise above 2V. This ensures that the part does not try to function until it has enough voltage to do so. During this time, the 1V precharge circuitry is also ac- tive and forces 1V through 100k nominal resistors to the SDA and SCL pins. Because the I/O card is being plugged into a live backplane, the voltage on the backplane SDA and SCL busses may be anywhere between 0V and VCC. Precharging the SCL and SDA pins to 1V minimizes the worst-case voltage differential these pins will see at the moment of connection, therefore minimizing the amount of disturbance caused by the I/O card. Once the LTC4300A comes out of UVLO, it assumes that SDAIN and SCLIN have been inserted into a live system and that SDAOUT and SCLOUT are being powered up at the same time as itself. Therefore, it looks for either a stop bit or bus idle condition on the backplane side to indicate the completion of a data transaction. When either one occurs, the part also verifies that both the SDAOUT and SCLOUT voltages are high. When all of these conditions are met, the input-to-output connection circuitry is activated, joining the SDA and SCL busses on the I/O card with those on the backplane, and the rise time accelerators are enabled. Connection Circuitry Once the connection circuitry is activated, the functionality of the SDAIN and SDAOUT pins is identical. A low forced on either pin at any time results in both pin voltages being low. For proper operation, logic low input voltages should be no higher than 0.4V with respect to the ground pin voltage of the LTC4300A. SDAIN and SDAOUT enter a logic high state only when all devices on both SDAIN and SDAOUT release high. The same is true for SCLIN and SCLOUT. This important feature ensures that clock stretching, clock synchronization, arbitration and the acknowledge protocol always work, regardless of how the devices in the system are tied to the LTC4300A. |
Similar Part No. - LTC4300A-1_15 |
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Similar Description - LTC4300A-1_15 |
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