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HD74LS373RPEL Datasheet(PDF) 3 Page - Renesas Technology Corp |
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HD74LS373RPEL Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 10 page Rev.2.00, Feb.18.2005, page 1 of 7 HD74LS373 Octal D-type Transparent Latches (with three-state outputs) REJ03D0482–0200 Rev.2.00 Feb.18.2005 The HD74LS373, 8-bit register features totem-pole three-state outputs designed specifically for driving highly- capacitive or relatively low-impedance loads. The high-impedance third state and increased high-logic-level drive provide this register with the capacity of being connected directly to and driving the bus lines in a bus-organized system without need for interface or pull-up components. They are particularly attractive for implementing buffer registers, I/O ports, bidirectional bus drivers, and working registers. The eight latches are transparent D-type latches meaning that while the enable (G) is high the Q outputs will follow the data (D) inputs. When the enable is taken low the output will be latched at the level of the data that was setup. Features • Ordering Information Part Name Package Type Package Code (Previous Code) Package Abbreviation Taping Abbreviation (Quantity) HD74LS373P DILP-20 pin PRDP0020AC-B (DP-20NEV) P — HD74LS373FPEL SOP-20 pin (JEITA) PRSP0020DD-B (FP-20DAV) FP EL (2,000 pcs/reel) HD74LS373RPEL SOP-20 pin (JEDEC) PRSP0020DC-A (FP-20DBV) RP EL (1,000 pcs/reel) Note: Please consult the sales office for the above package availability. Pin Arrangement (Top view) VCC GND Output Control 1Q 1D 2D 2Q 3Q 3D 4D 4Q 8Q 7D 8D 7Q 6D 6Q 5D Enable G 5Q 20 17 18 19 15 16 1 2 3 4 5 6 7 14 8 9 10 11 12 13 Q D G OE Q D G OE Q D G OE Q D G OE Q D G OE Q D G OE Q D G OE Q D G OE |
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