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HD74LV32ARPEL Datasheet(PDF) 3 Page - Renesas Technology Corp |
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HD74LV32ARPEL Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 11 page Rev.3.00 Jun. 01, 2004 page 1 of 8 HD74LV32A Quad. 2-input OR Gates REJ03D0311–0300Z (Previous ADE-205-243A (Z)) Rev.3.00 Jun. 01, 2004 Description The HD74LV32A has four two-input OR gates in a 14-pin package. Low-voltage and high-speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • V CC = 2.0 V to 5.5 V operation • All inputs V IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs V O (Max.) = 5.5 V (@VCC = 0 V) • Typical V OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical V OH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) • Output current ±6 mA (@V CC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV32AFPEL SOP–14 pin(JEITA) FP–14DAV FP EL (2,000 pcs/reel) HD74LV32ARPEL SOP–14 pin(JEDEC) FP–14DNV RP EL (2,500 pcs/reel) HD74LV32ATELL TSSOP–14 pin TTP–14DV T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs AB Output Y HX H XH H LL L Note: H: High level L: Low level X: Immaterial |
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