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HD74LV4040AFPEL Datasheet(PDF) 3 Page - Renesas Technology Corp |
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HD74LV4040AFPEL Datasheet(HTML) 3 Page - Renesas Technology Corp |
3 / 13 page Rev.2.00 Jul. 20, 2004 page 1 of 10 HD74LV4040A 12-stage Binary Counter REJ03D0337–0200Z (Previous ADE-205-282 (Z)) Rev.2.00 Jul. 20, 2004 Description The HD74LV4040A is a 12 stage counter. This device is incremented on the falling edge (negative transition) of the input clock, and all its output is reset to a low level by applying a logical high on its reset input. Low-voltage and high- speed operation is suitable for the battery-powered products (e.g., notebook computers), and the low-power consumption extends the battery life. Features • V CC = 2.0 V to 5.5 V operation • All inputs V IH (Max.) = 5.5 V (@VCC = 0 V to 5.5 V) • All outputs V O (Max.) = 5.5 V (@VCC = 0 V) • Typical V OL ground bounce < 0.8 V (@VCC = 3.3 V, Ta = 25°C) • Typical V OH undershoot > 2.3 V (@VCC = 3.3 V, Ta = 25°C) • Output current ±6 mA (@V CC = 3.0 V to 3.6 V), ±12 mA (@VCC = 4.5 V to 5.5 V) • Ordering Information Part Name Package Type Package Code Package Abbreviation Taping Abbreviation (Quantity) HD74LV4040AFPEL SOP–16 pin (JEITA) FP–16DAV FP EL (2,000 pcs/reel) HD74LV4040ARPEL SOP–16 pin (JEDEC) FP–16DNV RP EL (2,500 pcs/reel) HD74LV4040ATELL TSSOP–16 pin TTP–16DAV T ELL (2,000 pcs/reel) Note: Please consult the sales office for the above package availability. Function Table Inputs Output CLK CLR Qn ↑ L Remains unchanged ↓ L Changed X H All outputs low Note: H: High level L: Low level X: Immaterial ↑: Low to high transition ↓: High to low transition |
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