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AN2674 Datasheet(PDF) 3 Page - STMicroelectronics |
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AN2674 Datasheet(HTML) 3 Page - STMicroelectronics |
3 / 22 page AN2674 Power integrity Doc ID 14204 Rev 2 3/22 1 Power integrity One of the most important requirements of a reliable high-speed memory interface, and most commonly underestimated, is a low impedance, wide bandwidth power supply at the power and ground balls of the devices. Achieving the necessary performance requires the minimizing of all parasitic inductances found in power delivery and grounding connections, exploiting various techniques to provide low impedance paths, and attention to controlling plane resonances. A solid unbroken ground plane located close to the high-speed devices in the PCB layer stack is critical. The ground plane must not have large gaps anywhere in the area of the interface. Be especially aware of overlapping anti-pads that can create an extended gap in the internal plane layers. A power plane closely spaced to the ground plane greatly aids the high-frequency decoupling by providing a low inductance path between a capacitor and the device's power balls. All high-frequency decoupling capacitors should utilize a low-inductance layout. 1.1 PCB stack up Stack up should include a closely spaced power/ground plane pair. A minimum of 6 layers is necessary. Recommendation: Layer 1: signal Layer 2: ground plane, unbroken Layer 3: power plane/islands, signals Layer 4: signal/power routing Layer 5: ground plane, unbroken Layer 6: signal Dielectric thickness should be selected to support required signal trace characteristic impedances and power plane capacitance/inductance. Resonance analysis should be performed on all plane cavities. 1.2 Via padstack Via padstack dimensions should support density requirements. Anti-pad diameter should be small enough to allow an adequate copper web between clearance holes of adjacent vias, and still meet PCB fabrication tolerances. 1.3 Part orientation and placement The DRAM placement and orientation should be given priority over other unassociated components in order to minimize trace lengths. Closely following the signal trace routing guidelines allows trace lengths to be reduced. |
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